Patent application number | Description | Published |
20110144939 | COMPUTERISED STORAGE SYSTEM COMPRISING ONE OR MORE REPLACEABLE UNITS FOR MANAGING TESTING OF ONE OR MORE REPLACEMENT UNITS - A method, apparatus and software is disclosed, for use in a computerised storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode. | 06-16-2011 |
20120239983 | COMPUTERISED STORAGE SYSTEM COMPRISING REPLACEABLE UNITS FOR MANAGING TESTING OF REPLACEMENT UNITS - A method for use in a computerized storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode. | 09-20-2012 |
20130080408 | AUTOMATED SELECTION OF FUNCTIONS TO REDUCE STORAGE CAPACITY BASED ON PERFORMANCE REQUIREMENTS - A plurality of functions to configure a unit of a storage volume is maintained, wherein each of the plurality of functions, in response to being applied to the unit of the storage volume, configures the unit of the storage volume differently. Statistics are computed on growth rate of data and access characteristics of the data stored in the unit of the storage volume. A determination is made as to which of the plurality of functions to apply to the unit of the storage volume, based on the computed statistics. | 03-28-2013 |
20130080728 | AUTOMATED SELECTION OF FUNCTIONS TO REDUCE STORAGE CAPACITY BASED ON PERFORMANCE REQUIREMENTS - A plurality of functions to configure a unit of a storage volume is maintained, wherein each of the plurality of functions, in response to being applied to the unit of the storage volume, configures the unit of the storage volume differently. Statistics are computed on growth rate of data and access characteristics of the data stored in the unit of the storage volume. A determination is made as to which of the plurality of functions to apply to the unit of the storage volume, based on the computed statistics. | 03-28-2013 |
20140089740 | COMPUTERISED STORAGE SYSTEM COMPRISING REPLACEABLE UNITS FOR MANAGING TESTING OF REPLACEMENT UNITS - A method for use in a computerized storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode. | 03-27-2014 |
20140136147 | Determining System Performance - A system comprises one or more components, such as a processing device and/or a storage device and a monitoring element that is connected to at least one of the components. A mechanism of determining performance in the system determines, for each component, a maximum achievable performance for a component for a specific metric, determines a maximum performance for the component for the specific metric, given the current system configuration, determines a current performance for the component for the specific metric, and provides the determined performance measurements to the monitoring element. | 05-15-2014 |
Patent application number | Description | Published |
20110056655 | Dual-Fluid Heat Exhanger - An integrated circuit dual-fluid heat exchanger has a housing containing first and second immiscible fluids. A heat-introducing base element contacts the first fluid. A heat-receiving surface on the base element is configured for interfacial contact with a heat-radiating surface of an integrated circuit device. A heat-removing condenser element contacts the second fluid, or is separated therefrom by a gap. The first and second fluids are selected to controllably remove heat from the integrated circuit device by forming heated mass units of the first fluid that migrate through the second fluid and come into contact with the condenser element, where they are cooled and allowed to return to the base element. A heat-expulsion portion on the condenser element is configured to dissipate heat removed by the condenser element to an exterior environment outside the heat exchanger. | 03-10-2011 |
20110303403 | Flexible Heat Exchanger - An embodiment of the invention comprises a method for constructing a heat exchanger for cooling one or more semiconductor components. The method comprises the step of providing first and second planar sheets of specified thermally conductive metal foil, wherein each of the sheets has and exterior side and an interior side. The method further comprises forming one or more thermal contact nodes (TCNs) in the first sheet, wherein each TCN extends outward from the exterior side of the first sheet, and comprises a planar contact member and one or more side sections, the side sections respectively including resilient components that enable the contact member of the TCN to move toward and away from the exterior side of the first sheet, and the side sections and contact member of a TCN collectively forming a coolant chamber. Channel segments are configured along the interior side of the first sheet, wherein each channel extends between the coolant chambers and two TCNs, or between the coolant chamber of a TCN and an input port or output port, selectively. The method further comprises joining the interior side of the second sheet to the interior side of the first sheet, in order to form a sealed flow path that includes each channel segment, and enables liquid coolant to flow into and out of the coolant chamber of each TCN. | 12-15-2011 |
20110310566 | FLUX-FREE DETACHABLE THERMAL INTERFACE BETWEEN AN INTERGRATED CIRCUIT DEVICE AND A HEAT SINK - A thermal flow material-free thermally conductive interface between a mounted integrated circuit device and a heat sink that comprises a mounted integrated circuit device, a heat sink vertically disposed over the device, a vertically compressible thermally conductive member unattachably disposed between the device and the heat sink, and an unattached frame member horizontally enclosing the compressible member. | 12-22-2011 |
20120138269 | DUPLEX FLEXIBLE HEAT EXCHANGER - A method and system for cooling an electrical heat source is disclosed. A heat exchanger has two principal sub-assemblies. A closed-loop fluid flow is provided through a second sub-assembly, disposed next to a heat source. An open-loop fluid flow is provided though a first sub-assembly in communication with a second sub-assembly. Each of the first and second sub-assemblies has a rotational element. The fluid flow entering the first sub-assembly rotates the first rotational element, and magnetic communication between the rotational elements causes movement of the second rotational element, thereby achieving fluid movement within the second sub-assembly. Operationally, the closed-loop sub-assembly removes heat from the heat source and transfers it to the open-loop sub-assembly for subsequent heat transfer in a downstream fluid flow. | 06-07-2012 |
20120312510 | Automatic In Situ Coolant Flow Control in LFT Heat Exchanger - An embodiment of the invention is directed to coolant flow control apparatus, in association with a liquid flow through heat exchanger situated to cool one or more electronic or other device. The apparatus comprises a first input channel for carrying liquid coolant to a first input of the heat exchanger, and further comprises a flow control device positioned along a flow path that includes the first input channel. The flow control device is provided with a gating element supported for selected movement across the flow path, in order to selectively vary the amount of coolant moving through the flow path. The apparatus further include an actuator located in the flow control device that comprises a metal component which is directly tied to the gating element, wherein the metal component changes its shape in response to specified changes in coolant temperature, and a given change in the shape of the metal component acts to selectively move the gating element with respect to the flow path. | 12-13-2012 |
20130060813 | PRODUCT TRACKING SYSTEM - A method, programmed medium and system are disclosed which provide increased secure tracking of materials and products through the use of a unique coding scheme. The coding scheme contains a unique security code identifier issued by a sole certification agency, and includes a non-coded scheme for public information, and a coded scheme for private information regarding the sourcing and development of materials and products. The disclosure provides for full tracking of a product throughout the supply chain by only certified participants. The disclosed system allows for increased secure tracking of materials and products, and allows for access to greater amounts of information at various stages of manufacture and/or assembly regarding a given material or product. | 03-07-2013 |
20130324952 | Ostomy Appliance Wear Time Prediction - Use of and performance of ostomy appliances are enhanced by providing one or more sensors to an ostomy pouch; collecting sensor data by sensors to form a history of events impinging on the ostomy pouch and conditions of the pouch over time; comparing the sensor data to historical sensor data for a similar ostomy pouch to predict a reduction in nominal wear time; and notifying a user of the predicted reduction in nominal wear time. | 12-05-2013 |
20140332198 | AUTOMATIC IN SITU COOLANT FLOW CONTROL IN LFT HEAT EXCHANGER - In association with a liquid flow through a heat exchanger situated to remove heat from electronic devices, a coolant flow control apparatus is provided. The coolant flow control apparatus comprises a first input channel for carrying liquid coolant to a first input of the heat exchanger; a flow control device positioned along a flow path that includes the first input channel, the flow control device, in response to a temperature of coolant proximate to the flow control device, is operable to enable or to prevent coolant flow along the first input channel into the heat exchanger; a second input channel for continuously carrying liquid coolant to a second input of the heat exchanger, during both times when the flow control device is enabling and is preventing the coolant flow along the first input channel into the heat exchanger; and an output channel for carrying coolant away from the heat exchanger. | 11-13-2014 |
20140370469 | UTILIZING APPLIANCE OPERATING PATTERNS TO DETECT COGNITIVE IMPAIRMENT - A method, system or computer usable program product for detecting a change in appliance operating patterns as an indication of cognitive impairment including monitoring a first operating pattern for an appliance by a user to establish a baseline operating pattern; and responsive to detecting a second operating pattern for the appliance by the user deviating from the established baseline operating pattern exceeding a threshold, providing an indication of a possible cognitive impairment of the user. | 12-18-2014 |
Patent application number | Description | Published |
20120215987 | BROADCAST PROTOCOL FOR A NETWORK OF CACHES - A method for managing caches, including: broadcasting, by a first cache agent operatively connected to a first cache and using a first physical network, a first peer-to-peer (P2P) request for a memory address; issuing, by a second cache agent operatively connected to a second cache and using a second physical network, a first response to the first P2P request based on a type of the first P2P request and a state of a cacheline in the second cache corresponding to the memory address; issuing, by a third cache agent operatively connected to a third cache, a second response to the first P2P request; and upgrading, by the first cache agent and based on the first response and the second response, a state of a cacheline in the first cache corresponding to the memory address. | 08-23-2012 |
20140040526 | COHERENT DATA FORWARDING WHEN LINK CONGESTION OCCURS IN A MULTI-NODE COHERENT SYSTEM - Systems and methods for efficient data transport across multiple processors when link utilization is congested. In a multi-node system, each of the nodes measures a congestion level for each of the one or more links connected to it. A source node indicates when each of one or more links to a destination node is congested or each non-congested link is unable to send a particular packet type. In response, the source node sets an indication that it is a candidate for seeking a data forwarding path to send a packet of the particular packet type to the destination node. The source node uses measured congestion levels received from other nodes to search for one or more intermediate nodes. An intermediate node in a data forwarding path has non-congested links for data transport. The source node reroutes data to the destination node through the data forwarding path. | 02-06-2014 |
20140040697 | USING A DATA ECC TO DETECT ADDRESS CORRUPTION - A system for detecting an address or data error in a memory system. During operation, the system stores a data block to an address by: calculating a hash of the address; using the calculated hash and data bits from the data block to compute ECC check bits; and storing the data block containing the data bits and the ECC check bits at the address. During a subsequent retrieval operation, the memory system uses the address to retrieve the data block containing the data bits and ECC check bits. Next, the system calculates a hash of the address and uses the calculated hash and the data bits to compute ECC check bits. Finally, the system compares the computed ECC check bits with the retrieved ECC check bits to determine whether an error exists in the address or data bits, or if a data corruption indicator is set. | 02-06-2014 |
20140075163 | LOAD-MONITOR MWAIT - Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction. | 03-13-2014 |
20140089591 | SUPPORTING TARGETED STORES IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM - The present embodiments provide a system for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor in the shared-memory multiprocessor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. The system includes an interface, such as an application programming interface (API), and a system call interface or an instruction-set architecture (ISA) that provides access to a number of mechanisms for supporting targeted stores. These mechanisms include a thread-location mechanism that determines a location near where a thread is executing in the shared-memory multiprocessor, and a targeted-store mechanism that targets a store to a location (e.g., cache memory) in the shared-memory multiprocessor. | 03-27-2014 |
20140095810 | MEMORY SHARING ACROSS DISTRIBUTED NODES - A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, load and store instructions that target the mirrored memory portion of a sharer node are trapped, and store instructions that target the shared memory portion of a home node are trapped. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no “dirty” data is transferred between sharer nodes. As a result, the failure of one node will not cause the failure of another node or the failure of the entire system. | 04-03-2014 |
20140181420 | DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY - A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories. | 06-26-2014 |
20140215157 | MONITORING MULTIPLE MEMORY LOCATIONS FOR TARGETED STORES IN A SHARED-MEMORY MULTIPROCESSOR - A system and method for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. More specifically, the disclosed embodiments provide a system that notifies a waiting thread when a targeted store is directed to monitored memory locations. During operation, the system receives a targeted store which is directed to a specific cache in a shared-memory multiprocessor system. In response, the system examines a destination address for the targeted store to determine whether the targeted store is directed to a monitored memory location which is being monitored for a thread associated with the specific cache. If so, the system informs the thread about the targeted store. | 07-31-2014 |
20140279894 | MEMORY SHARING ACROSS DISTRIBUTED NODES - A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, a special data value is used to indicate that data in a mirrored memory location is not valid. This enables a sharer node to know when to obtain valid data from a home node. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no “dirty” data is transferred between sharer nodes. Consequently, the failure of one node will not cause the failure of another node or the failure of the entire system. | 09-18-2014 |
20140281237 | BROADCAST CACHE COHERENCE ON PARTIALLY-ORDERED NETWORK - A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request. | 09-18-2014 |
20150039940 | PROCESSOR DESIGN VERIFICATION - A system and method for verifying that a processor design having caches conforms to a specific memory model. The caches might not be maintained coherent in real time. Specifically, the system and method make use of a checker that conforms to the memory model, a time-stamping scheme, and a store buffering scheme to identify a bug(s) in the processor design that violates the memory model and/or loads an incorrect value in response to a load instruction. | 02-05-2015 |
Patent application number | Description | Published |
20080302763 | VACUUM FAULT INTERRUPTER - Exemplary vacuum fault interrupters are described. | 12-11-2008 |
20080302764 | Contact backing for a vacuum interrupter - Exemplary contact backings for vacuum interrupters are described. | 12-11-2008 |
20090077793 | High Voltage Operating Rod Sensor and Method of Making the Same - Methods and system for making and using vacuum switching devices are disclosed. A vacuum switching device has an operating rod for actuating a movable electrical contact within the device. The operating rod may be a hollow epoxy glass tube with an electrical sensor disposed within it, and there may be an elastomeric polymer filling compound disposed within the tube and encasing the sensor. The operating rod may be attached to the movable electrical contact on one end by a steel end-fitting that has been press-fit into the tube and secured with at least one cross pin. In this way, a very secure electromechanical connection may be made between the operating rod and the rest of the vacuum switching device, and the sensor is protected from shock associated with the operation of the device. Moreover, the vacuum switching device is compact and easy to construct. | 03-26-2009 |
20100192360 | AXIAL MAGNETIC FIELD VACUUM FAULT INTERRUPTER - An improved vacuum interrupter is disclosed. The vacuum interrupter includes a ring-shaped structure placed between a contact support structure and an electrical contact associated with the contact support structure. A resistivity of the ring-shaped structure is higher than that of the contact support structure, so that current traversing the ring-shaped structure on its way from the contact support structure to the electrical contact is evenly distributed. The ring-shaped structure may be fit into an end portion of the contact support structure, the end portion having a diameter less than an outer diameter of the support structure, but greater than an inner diameter of the support structure. Alternatively, the end portion may be used without the ring-shaped portion, in which case the electrical contact may be shaped to fit into the end portion. | 08-05-2010 |