Patent application number | Description | Published |
20090127587 | TUNABLE ANTIFUSE ELEMENTS - A tunable antifuse element ( | 05-21-2009 |
20090267127 | Single Poly NVM Devices and Arrays - A single-poly non-volatile memory includes a PMOS select transistor ( | 10-29-2009 |
20090290437 | CIRCUIT FOR AND AN ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL AND A PROCESS OF FORMING THE ELECTRONIC DEVICE - A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device. | 11-26-2009 |
20100109090 | CMOS LATCH-UP IMMUNITY - Latch-up of CMOS devices ( | 05-06-2010 |
20110101465 | CMOS DEVICE STRUCTURES - Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd). | 05-05-2011 |
20110261500 | BACK END OF LINE METAL-TO-METAL CAPACITOR STRUCTURES AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures. The first metal layer provides an intralayer electrical interconnection among the second plurality of vertical conductive structures, wherein each vertically-aligned region has a vertical conductive structure of the second plurality of vertical conductive structures disposed therein. | 10-27-2011 |
20110299337 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-08-2011 |
20130270606 | Semiconductor Device with Integrated Breakdown Protection - A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path. | 10-17-2013 |
20130270635 | Semiconductor Device with False Drain - An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic. | 10-17-2013 |
20130341717 | Semiconductor Device with Floating RESURF Region - A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap. | 12-26-2013 |
20140001473 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001477 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001546 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH A CURRENT CARRYING REGION AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001548 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001549 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001594 | SCHOTTKY DIODE WITH LEAKAGE CURRENT CONTROL STRUCTURES | 01-02-2014 |
20140061715 | ZENER DIODE DEVICE AND FABRICATION - A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region. | 03-06-2014 |
20140061731 | Tunable Schottky Diode - A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region. | 03-06-2014 |
20140117468 | METHODS AND INTEGRATED CIRCUIT PACKAGE FOR SENSING FLUID PROPERTIES - An integrated circuit package for sensing fluid properties includes: a substrate made of semiconductor material; a fluid property measurement circuit formed on the substrate; and a sensor circuit coupled to the fluid property measurement circuit within a same integrated circuit package. The sensor circuit is configured to generate a field that interacts with the fluid. The fluid property measurement circuit is configured to determine a change in a property of the sensor circuit as results from the field interacting with the fluid and is further configured to determine a property of the fluid based on the change in the property of the sensor circuit. | 05-01-2014 |
20140242762 | Tunable Schottky Diode with Depleted Conduction Path - A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed. | 08-28-2014 |
20140252470 | Semiconductor Device with Integrated Electrostatic Discharge (ESD) Clamp - A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively. | 09-11-2014 |
20140252472 | SEMICONDUCTOR DEVICE WITH INCREASED SAFE OPERATING AREA - A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well. | 09-11-2014 |
20140375370 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-25-2014 |
20150085407 | STACKED PROTECTION DEVICES AND RELATED FABRICATION METHODS - Protection device structures and related fabrication methods and devices are provided. An exemplary device includes a first interface, a second interface, a first protection circuitry arrangement coupled to the first interface, and a second protection circuitry arrangement coupled between the first protection circuitry arrangement and the second interface. The second protection circuitry arrangement includes a first transistor and a diode coupled to the first transistor, wherein the first transistor and the diode are configured electrically in series between the first protection circuitry arrangement and the second interface. | 03-26-2015 |