Patent application number | Description | Published |
20110145318 | INTERACTIVE ANALYTICS PROCESSING - An end-to-end record, request, response token-based protocol is used to facilitate processing of client jobs. This allows the client to forward analytical tasks of a job directly to an analytics cluster and to record an indication of such at a server. The accelerators of the cluster to perform the tasks are specified in a token provided by the server to the client. | 06-16-2011 |
20110145366 | CONCURRENT EXECUTION OF REQUEST PROCESSING AND ANALYTICS OF REQUESTS - Request processing within a computing environment is facilitated. Request processing and analytics processing for the request are performed substantially concurrently in order to improve efficiency of request execution. The analytics processing is at least commenced, and may complete, prior to receiving an indication of success or failure of the request processing. If request processing fails, analytics processing ceases, if not already complete, and results of the analytic processing are not used. | 06-16-2011 |
20110145429 | MULTI-GRANULAR STREAM PROCESSING - Stream processing is facilitated by distributing responsibility for processing the stream to multiple components of a computing environment. A programmable unit receives one or more streams and determines the operations to be performed for the one or more streams and which components of the computing environment are to perform those operations. It forwards data relating to the one or more streams to one or more components of the computing environment for processing and/or information purposes. | 06-16-2011 |
20130007412 | UNIFIED, WORKLOAD-OPTIMIZED, ADAPTIVE RAS FOR HYBRID SYSTEMS - A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes managing workloads on a first processor with a first processor architecture by an agent process executing on a second processor with a second processor architecture. The method proceeds by activating redundant computation on the second processor by the agent process. The method continues by performing a same computation from a workload of the workloads at least twice. Finally, the method includes comparing results of the same computation. In this embodiment the first processor is coupled the second processor by a network, and the first processor architecture and second processor architecture are different architectures. | 01-03-2013 |
20130007759 | UNIFIED, WORKLOAD-OPTIMIZED, ADAPTIVE RAS FOR HYBRID SYSTEMS - A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes performing a first data computation by a first set of processors, the first set of processors having a first computer processor architecture. The method continues by performing a second data computation by a second processor coupled to the first set of processors, the second processor having a second computer processor architecture, the first computer processor architecture being different than the second computer processor architecture. Finally, the method includes dynamically allocating computational resources of the first set of processors and the second processor based on at least one metric while the first set of processors and the second processor are in operation such that the accuracy and processing speed of the first data computation and the second data computation are optimized. | 01-03-2013 |
20130097407 | UNIFIED, WORKLOAD-OPTIMIZED, ADAPTIVE RAS FOR HYBRID SYSTEMS - A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes managing workloads on a first processor with a first processor architecture by an agent process executing on a second processor with a second processor architecture. The method proceeds by activating redundant computation on the second processor by the agent process. The method continues by performing a same computation from a workload of the workloads at least twice. Finally, the method includes comparing results of the same computation. In this embodiment the first processor is coupled the second processor by a network, and the first processor architecture and second processor architecture are different architectures. | 04-18-2013 |
20130097611 | UNIFIED, WORKLOAD-OPTIMIZED, ADAPTIVE RAS FOR HYBRID SYSTEMS - A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes performing a first data computation by a first set of processors, the first set of processors having a first computer processor architecture. The method continues by performing a second data computation by a second processor coupled to the first set of processors, the second processor having a second computer processor architecture, the first computer processor architecture being different than the second computer processor architecture. Finally, the method includes dynamically allocating computational resources of the first set of processors and the second processor based on at least one metric while the first set of processors and the second processor are in operation such that the accuracy and processing speed of the first data computation and the second data computation are optimized. | 04-18-2013 |
20130191848 | Distributed Function Execution for Hybrid Systems - A system for distributed function execution, the system includes a host in operable communication with an accelerator. The system is configured to perform a method including processing an application by the host and distributing at least a portion of the application to the accelerator for execution. The method also includes instructing the accelerator to create a buffer on the accelerator, instructing the accelerator to execute the portion of the application, wherein the accelerator writes data to the buffer and instructing the accelerator to transmit the data in the buffer to the host before the application requests the data in the buffer. The accelerator aggregates the data in the buffer before transmitting the data to the host based upon one or more runtime conditions in the host. | 07-25-2013 |
20130191849 | DISTRIBUTED FUNCTION EXECUTION FOR HYBRID SYSTEMS - A method includes processing an application by a host including one or more processors and distributing at least a portion of the application to an accelerator for execution. The method includes instructing the accelerator to create a buffer on the accelerator and instructing the accelerator to execute the portion of the application, wherein the accelerator writes data to the buffer. The method also includes instructing the accelerator to transmit the data in the buffer to the host before the application requests the data in the buffer. The accelerator aggregates the data in the buffer before transmitting the data to the host based upon one or more runtime conditions in the host. | 07-25-2013 |
Patent application number | Description | Published |
20110320523 | SPECULATIVE AND COORDINATED DATA ACCESS IN A HYBRID MEMORY SERVER - A method, accelerator system, and computer program product, for prefetching data from a server system in an out-of-order processing environment. A plurality of prefetch requests associated with one or more given data sets residing on the server system are received from an application on the server system. Each prefetch request is stored in a prefetch request queue. A score is assigned to each prefetch request. A set of the prefetch requests are selected from the prefetch queue that comprise a score above a given threshold. A set of data, for each prefetch request in the set of prefetch requests, is prefetched from the server system that satisfies each prefetch request, respectively. | 12-29-2011 |
20110320804 | DATA ACCESS MANAGEMENT IN A HYBRID MEMORY SERVER - A method, accelerator system, and computer program access data in an out-of-core processing environment. A data access configuration is received from a server system managing a plurality of data sets. A determination is made that data sets retrieved from the server system are to be stored locally based on the data access configuration. A request to interact with a given data set is received from a user client. At least a portion of the given data set is retrieved from the server system. The at least a portion of the given data set is stored locally a memory based on the data access configuration that has been received. | 12-29-2011 |
20120096109 | Hierarchical Pre-fetch Pipelining in a Hybrid Memory Server - A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on the server system are received from a set of accelerator systems. A set of data is prefetched from a memory system residing at the server system for at least one prefetch request in the set of prefetch requests. The set of data satisfies the at least one prefetch request. The set of data that has been prefetched is sent to at least one accelerator system, in the set of accelerator systems, associated with the at least one prefetch request. | 04-19-2012 |
20120102138 | Multiplexing Users and Enabling Virtualization on a Hybrid System - A method, hybrid server system, and computer program product, support multiple users in an out-of-core processing environment. At least one accelerator system in a plurality of accelerator systems is partitioned into a plurality of virtualized accelerator systems. A private client cache is configured on each virtualized accelerator system in the plurality of virtualized accelerator systems. The private client cache of each virtualized accelerator system stores data that is one of accessible by only the private client cache and accessible by other private client caches associated with a common data set. Each user in a plurality of users is assigned to a virtualized accelerator system from the plurality of virtualized accelerator systems. | 04-26-2012 |
20120117312 | Hybrid Server with Heterogeneous Memory - A method, hybrid server system, and computer program product, for managing access to data stored on the hybrid server system. A memory system residing at a server is partitioned into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems. The set of accelerator systems are communicatively coupled to the server. The memory system comprises heterogeneous memory types. A data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems is identified. The data set is transformed from a first format to a second format, wherein the second format is a format required by the at least one accelerator system. | 05-10-2012 |
20130073668 | SPECULATIVE AND COORDINATED DATA ACCESS IN A HYBRID MEMORY SERVER - A method, accelerator system, and computer program product, for prefetching data from a server system in an out-of-order processing environment. A plurality of prefetch requests associated with one or more given data sets residing on the server system are received from an application on the server system. Each prefetch request is stored in a prefetch request queue. A score is assigned to each prefetch request. A set of the prefetch requests are selected from the prefetch queue that comprise a score above a given threshold. A set of data, for each prefetch request in the set of prefetch requests, is prefetched from the server system that satisfies each prefetch request, respectively. | 03-21-2013 |
20130212376 | DATA ACCESS MANAGEMENT IN A HYBRID MEMORY SERVER - Once or more embodiments manage access to data by accelerator systems in an out-of-core processing environment. In one embodiment, a request from an accelerator system is received for access to a given data set. An access context associated with the given data set is determined. The accelerator system is dynamically configured, based on the access context that has been determined, based on the access context that has been determined, to one of access the given data set directly from the server system; locally store a portion of the given data set in a memory; and locally store all of the given data set in the memory. | 08-15-2013 |
Patent application number | Description | Published |
20150100513 | Customer Controlled Management of Shipments - Computer program products, methods, systems, apparatus, and computing entities are provided for customer controlled management of shipments. For example, customers can define handling identifiers to determine how items should be handled based on the handling identifier. Further, customers can define refund classifications to determine when refunds should be initiated. | 04-09-2015 |
20150100514 | Customer Controlled Management of Shipments - Computer program products, methods, systems, apparatus, and computing entities are provided for customer controlled management of shipments. For example, customers can define handling identifiers to determine how items should be handled based on the handling identifier. Further, customers can define refund classifications to determine when refunds should be initiated. | 04-09-2015 |
20150235171 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING INTELLIGENT VISIBILITY ACROSS AN OUTCOME-BASED SERVICE CYCLE INFRASTRUCTURE - Various embodiments provide a service cycle management system for intelligently evaluating one or more parameters of a reverse service cycle loop within a supply chain management infrastructure. The system comprises one or more processors configured to: receive the real-time data comprising one or more parameters associated with execution of one or more service tasks; retrieve the simulation data from the one or more memory storage areas; dynamically compare one or more parameters within the real-time data against corresponding one or more parameters within the simulation data to identify one or more discrepancies there-between; in response to identifying one or more discrepancies, and generating one or more representations thereof, so as to inform one or more users of the system of one or more areas for focusing future initiatives. Associated computer program products and computer implemented methods are also provided. | 08-20-2015 |
20150235287 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR ENABLING OUTCOME-BASED SERVICE CYCLE MANAGEMENT - Various embodiments provide a service cycle management system configured to: receive a first portion of input data comprising one or more requests from one or more holders of an asset; retrieve a second portion of the input data comprising one or more parameters associated with handling of the asset within the reverse cycle loop; calculate one or more optimal service tasks for handling of the asset based at least in part upon the service data and the one or more parameters defined by the holder; calculate one or more optimal service providers to perform the one or more optimal service tasks based at least in part upon the provider data, the one or more calculated optimal service tasks, and the one or more parameters defined by the holder. Associated computer program products and computer implemented methods are also provided. | 08-20-2015 |
20150269535 | CONCEPTS FOR REPAIR, SERVICE, PURCHASE, SALE OR TRADE-IN OF ITEMS - Embodiments of the present invention provide a repair or purchase program that may be associated with a common carrier. In various embodiments, one or more bids for a target item are received prior to receiving a listing for an item. After receiving the listing for the item, one or more relevant bids may be identified. Information associated with at least one of the identified bids may be provided. A user selection of one of the identified bids may be received. Completion of the transaction indicated by the user's selection may be facilitated. Associated methods, systems, and computer program products are provided. | 09-24-2015 |
20150269536 | CONCEPTS FOR REPAIR, SERVICE, PURCHASE, SALE OR TRADE-IN OF ITEMS - Embodiments of the present invention provide a repair or purchase program that may be associated with a common carrier. In various embodiments, one or more bids for a target item are received prior to receiving a listing for an item. After receiving the listing for the item, one or more relevant bids may be identified. Information associated with at least one of the identified bids may be provided. A user selection of one of the identified bids may be received. Completion of the transaction indicated by the user's selection may be facilitated. Associated methods, systems, and computer program products are provided. | 09-24-2015 |
Patent application number | Description | Published |
20090127587 | TUNABLE ANTIFUSE ELEMENTS - A tunable antifuse element ( | 05-21-2009 |
20090267127 | Single Poly NVM Devices and Arrays - A single-poly non-volatile memory includes a PMOS select transistor ( | 10-29-2009 |
20090290437 | CIRCUIT FOR AND AN ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL AND A PROCESS OF FORMING THE ELECTRONIC DEVICE - A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device. | 11-26-2009 |
20100109090 | CMOS LATCH-UP IMMUNITY - Latch-up of CMOS devices ( | 05-06-2010 |
20110101465 | CMOS DEVICE STRUCTURES - Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd). | 05-05-2011 |
20110261500 | BACK END OF LINE METAL-TO-METAL CAPACITOR STRUCTURES AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures. The first metal layer provides an intralayer electrical interconnection among the second plurality of vertical conductive structures, wherein each vertically-aligned region has a vertical conductive structure of the second plurality of vertical conductive structures disposed therein. | 10-27-2011 |
20110299337 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-08-2011 |
20130270606 | Semiconductor Device with Integrated Breakdown Protection - A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path. | 10-17-2013 |
20130270635 | Semiconductor Device with False Drain - An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic. | 10-17-2013 |
20130341717 | Semiconductor Device with Floating RESURF Region - A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap. | 12-26-2013 |
20140001473 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001477 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001546 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH A CURRENT CARRYING REGION AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001548 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001549 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001594 | SCHOTTKY DIODE WITH LEAKAGE CURRENT CONTROL STRUCTURES | 01-02-2014 |
20140061715 | ZENER DIODE DEVICE AND FABRICATION - A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region. | 03-06-2014 |
20140061731 | Tunable Schottky Diode - A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region. | 03-06-2014 |
20140117468 | METHODS AND INTEGRATED CIRCUIT PACKAGE FOR SENSING FLUID PROPERTIES - An integrated circuit package for sensing fluid properties includes: a substrate made of semiconductor material; a fluid property measurement circuit formed on the substrate; and a sensor circuit coupled to the fluid property measurement circuit within a same integrated circuit package. The sensor circuit is configured to generate a field that interacts with the fluid. The fluid property measurement circuit is configured to determine a change in a property of the sensor circuit as results from the field interacting with the fluid and is further configured to determine a property of the fluid based on the change in the property of the sensor circuit. | 05-01-2014 |
20140242762 | Tunable Schottky Diode with Depleted Conduction Path - A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed. | 08-28-2014 |
20140252470 | Semiconductor Device with Integrated Electrostatic Discharge (ESD) Clamp - A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively. | 09-11-2014 |
20140252472 | SEMICONDUCTOR DEVICE WITH INCREASED SAFE OPERATING AREA - A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well. | 09-11-2014 |
20140375370 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-25-2014 |
20150085407 | STACKED PROTECTION DEVICES AND RELATED FABRICATION METHODS - Protection device structures and related fabrication methods and devices are provided. An exemplary device includes a first interface, a second interface, a first protection circuitry arrangement coupled to the first interface, and a second protection circuitry arrangement coupled between the first protection circuitry arrangement and the second interface. The second protection circuitry arrangement includes a first transistor and a diode coupled to the first transistor, wherein the first transistor and the diode are configured electrically in series between the first protection circuitry arrangement and the second interface. | 03-26-2015 |
20150162417 | ZENER DIODE DEVICES AND RELATED FABRICATION METHODS - Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different. | 06-11-2015 |
20150316503 | Differential Pair Sensing Circuit Structures - A differential pair sensing circuit ( | 11-05-2015 |
20150333189 | ZENER DIODE DEVICES AND RELATED FABRICATION METHODS - Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different. | 11-19-2015 |
20150357324 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF - Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s). | 12-10-2015 |
20150380317 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF - Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s). | 12-31-2015 |
20160047775 | SENSING FIELD EFFECT TRANSISTOR DEVICES, SYSTEMS IN WHICH THEY ARE INCORPORATED, AND METHODS OF THEIR FABRICATION - Embodiments of sensing devices include one or more integrated circuit (IC) die, a housing, and a fluid barrier material. Each IC die includes an electrode-bearing surface and a contact surface. One of the die includes an SFET with a sensing electrode proximate to the electrode-bearing surface. The same or a different die includes a reference electrode proximate to the electrode-bearing surface. The die(s) also include IC contacts at the contact surface(s), and conductive structures coupled between the SFET, the reference electrode, and the IC contacts. The housing includes a mounting surface, and housing contacts formed at the mounting surface. The IC contacts are coupled to the housing contacts. The fluid barrier material is positioned between the mounting surface and the IC die. The fluid barrier material provides a fluid barrier between the IC and housing contacts and a space that encompasses the sensing electrode and the reference electrode. | 02-18-2016 |
20160099240 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) CLAMPING - A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region. | 04-07-2016 |
20160099349 | SEMICONDUCTOR DEVICE WITH NON-ISOLATED POWER TRANSISTOR WITH INTEGRATED DIODE PROTECTION - A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices. | 04-07-2016 |