Patent application number | Description | Published |
20080239184 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - A liquid crystal display device includes; gate lines disposed on a display region, data lines disposed on the display region, wherein the data lines intersect with, and are insulated from, the gate lines, a gate driver which drives the gate lines, a plurality of data drivers which generate a data voltage from an input power source voltage and supply the data voltage to the data lines, and a power source voltage supplying unit which supplies different power source voltages to each of the data drivers according to a distance of each data driver from the gate driver. | 10-02-2008 |
20100045710 | BACKLIGHT APPARATUS AND A LIQUID CRYSTAL DISPLAY INCLUDING THE SAME - A liquid crystal display includes a liquid crystal panel, a backlight unit, and a backlight control circuit. The liquid crystal panel displays an image. The backlight unit supplies light to the liquid crystal panel and includes a plurality of backlight blocks arranged in a matrix. The backlight control circuit controls the backlight unit. When the backlight control circuit turns on at least one of the backlight blocks, it turns off any remaining backlight blocks arranged in a same row of the backlight unit. | 02-25-2010 |
20100123653 | Apparatus for Providing Grayscale Voltages and Display Device Using the Same - An apparatus for providing grayscale voltages and a display device using the same are provided. The display device includes a grayscale voltage provider that provides grayscale voltages using a first reference voltage and a second reference voltage in accordance with a selection signal. A data driver applies data voltages to data lines using the grayscale voltages and an image signal. A gate driver successively provides a gate-on voltage to the gate lines. A display panel displays an image for each frame using the data voltages and the gate-on voltage. | 05-20-2010 |
Patent application number | Description | Published |
20090009497 | LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME - A liquid crystal display includes a liquid crystal panel, which receives a plurality of gate signals and a plurality of data signals to display an image, a gate driver and a signal supplier which supplies a first scan-start signal, a clock signal and a clock bar signal to the gate driver, the clock bar signal having an inverse phase to that of the clock signal, wherein the clock signal includes a maintenance period and first and second transition periods, the maintenance period is defined when the clock signal is maintained at a first level, the first and second transition periods defined from a point when the clock signal transitions to a second level from the first level and to a subsequent point when the clock signal transitions to the first level from the second level, the first scan-start signal is maintained at the second level during the first transition period. | 01-08-2009 |
20090303403 | DRIVING-VOLTAGE GENERATION APPARATUS AND LIQUID CRYSTAL DISPLAY HAVING THE SAME - A driving-voltage generation apparatus and a liquid crystal display (LCD) having the same are provided. The driving-voltage generation apparatus includes an input node coupled to an input voltage, a voltage converter configured to convert the input voltage into an output voltage and output the output voltage, and a voltage cutoff unit electrically connected between the input node and the voltage converter. The voltage cutoff unit is configured to sense the input voltage and selectively cut off the supply of the input voltage. | 12-10-2009 |
20120026448 | DISPLAY PANEL, DISPLAY APPARATUS HAVING THE SAME, AND METHOD THEREOF - A display panel includes a source-pad portion, a first source fan-out portion and source lines. The source-pad portion has a group of pads to which a driving signal is applied from an external source. The source fan-out portion has output lines that are extended from the group of pads and are formed to have an asymmetric structure. The source lines are extended from the output lines, and pixels of different colors are connected to each of the source lines. Accordingly, a unit pixel portion is formed to be perpendicular to each other and a fan-out portion is formed to have the asymmetric structure, so that a size of a printed circuit board is remarkably decreased. Thus, costs for manufacturing a display apparatus may be decreased. | 02-02-2012 |
Patent application number | Description | Published |
20130143463 | MANUFACTURING METHOD OF DISPLAY PANEL - A manufacturing method for a display panel includes: forming a first display panel including a plurality of pixel electrodes, gate lines and data lines connected to the pixel electrodes, a first pad unit connected to the gate lines, and a second pad unit connected to the data lines; forming a second display panel including a common electrode; forming a first short point connected to the first pad unit; forming a second short point connected to the second pad unit; adhering the first display panel and the second display panel; dividing the second display panel into a plurality of regions insulated from each other, a first region corresponding to the first short point, a second region corresponding to the second short point, and a third region; and applying a first voltage to the first region, a second voltage to the second region, and a third voltage to the third region. | 06-06-2013 |
20130194536 | LIQUID CRYSTAL DISPLAY - A liquid crystal display is provided. A liquid crystal display includes: a first substrate; a thin film transistor disposed on the first substrate; and a first electrode disposed on the thin film transistor and connected to an output terminal of the thin film transistor, wherein the first electrode includes a first region and a second region each including a plurality of minute branches separated from each other by open parts, portions of at least two minute branches among the plurality of minute branches are connected to form a plurality of minute plate branches, and wherein the minute plate branch has a wider width than a minute branch. | 08-01-2013 |
20130242239 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display including a partial plate electrode along with a minute pattern in pixel electrode thereby increasing the viewing angle and the lateral visibility of the liquid crystal display, as well as the response speed A step provider is provided to reinforce the control force of the liquid crystal molecules, thereby reducing the texture generated in the center of the pixel. | 09-19-2013 |
20140159068 | DISPLAY DEVICE - A display device includes: a substrate; a signal line on the substrate; a signal input line on the substrate and connected to a driver; a first insulating layer between the signal line and the signal input line; a second insulating layer on the signal line, the signal input line and the first insulating layer; an organic layer on the second insulating layer; a first contact hole defined in the organic layer, the first insulating layer and the second insulating layer and exposing the signal line; a second contact hole defined in the organic layer and the second insulating layer and exposing the signal input line; and a connecting member on the organic layer, and connecting the signal line and the signal input line to each other through the first contact hole and the second contact hole, respectively. | 06-12-2014 |
20140375936 | CURVED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A curved display device includes a thin film transistor display unit including a first insulation substrate; a common electrode display unit disposed opposite to the thin film transistor display unit and including a second insulation substrate; a liquid crystal layer disposed between the thin film transistor display unit and the common electrode display unit; and a plurality of color filters disposed on the first insulation substrate or the second insulation substrate, where each color filter includes an overlapping compensation region, which overlaps an adjacent color filter, and a non-overlapping region, which does not overlap the adjacent color filter, the overlapping compensation region defines a stepped region having a step height with the non-overlapping region. | 12-25-2014 |
20150015822 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a plurality of pixels, a lower substrate and an upper substrate facing each other, a liquid crystal layer disposed between the lower substrate and the upper substrate, a pixel electrode disposed on the lower substrate and including a plurality of sub-regions which differently controls an inclination direction of liquid crystal molecules included in the liquid crystal layer for a pixel of the plurality of pixels, and a gate line disposed on the lower substrate and including a portion which overlaps a boundary between adjacent sub-regions of the plurality of sub-regions of the pixel electrode. | 01-15-2015 |
20150036073 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a display substrate which includes a plurality of pixel areas and is curved in a first direction, an opposite substrate which faces the display substrate, is coupled to the display substrate, and is curved along the display substrate, and a liquid crystal layer disposed between the display substrate and the opposite substrate, where a plurality of domains are defined in each of the plurality of pixel areas, directions in which liquid crystal molecules of the liquid crystal layer are aligned are different from each other in at least two domains among the plurality of domains, and the plurality of domains is arranged in a second direction crossing the first direction. | 02-05-2015 |
Patent application number | Description | Published |
20120056178 | MULTI-CHIP PACKAGES - A multi-chip package may include a package substrate, a plurality of semiconductor chips and conductive connecting members. The semiconductor chips may be sequentially stacked on the package substrate. Each of the semiconductor chips may include a signal pad and a test pad. The conductive wires may be electrically connected between the signal pad of an upper semiconductor chip among the semiconductor chips and the package substrate via the test pad of a lower semiconductor chip under the upper semiconductor chip. The test pad may be converted into the dummy pad by cutting a fuse. | 03-08-2012 |
20130093080 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes. | 04-18-2013 |
20150031149 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes. | 01-29-2015 |
Patent application number | Description | Published |
20080303760 | ARRAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME - An array substrate of an LCD having: a gate line formed along a first direction; a data line formed along a second direction crossing the first direction; first and second pixel electrodes spaced apart from each other; a thin-film transistor includes a gate electrode connected to the gate line; a source electrode connected to the data line and partially overlapping the second pixel electrode; and a drain electrode connected to the first pixel electrode spaced apart from the second pixel electrode along the second direction. The source electrode or the gate electrode overlaps the second pixel electrode but the drain electrode does not overlap the second pixel electrode. Electrical coupling between the first and second pixel electrodes are avoided with such configuration. | 12-11-2008 |
20090167703 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A display panel and a method for manufacturing the same are disclosed. The display panel includes: a first substrate, a touch spacer formed on a first substrate, a common electrode formed on the touch spacer, a second substrate opposing the first substrate, a sensing electrode facing the touch spacer on the second substrate and an alignment layer on the sensing electrode or the touch spacer, wherein the alignment layer has a thickness equal to or less than 500 Å. | 07-02-2009 |
20090237365 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A display panel and a method for manufacturing the same are disclosed. The display panel includes: a first substrate, a touch spacer formed on a first substrate, a second substrate opposing the first substrate, a sensing electrode facing the touch spacer in the second substrate wherein the sensing electrode has a concave surface. | 09-24-2009 |
20120200815 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A display panel and a method for manufacturing the same are disclosed. The display panel includes: a first substrate, a touch spacer formed on a first substrate, a common electrode formed on the touch spacer, a second substrate opposing the first substrate, a sensing electrode facing the touch spacer on the second substrate and an alignment layer on the sensing electrode or the touch spacer, wherein the alignment layer has a thickness equal to or less than 500Å. | 08-09-2012 |
20130299831 | ARRAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME - An array substrate of an LCD having: a gate line formed along a first direction;a data line formed along a second direction crossing the first direction;first and second pixel electrodes spaced apart from each other;a thin-film transistor includes a gate electrode connected to the gate line; a source electrode connected to the data line and partially overlapping the second pixel electrode; and a drain electrode connected to the first pixel electrode spaced apart from the second pixel electrode along the second direction. The source electrode or the gate electrode overlaps the second pixel electrode but the drain electrode does not overlap the second pixel electrode. Electrical coupling between the first and second pixel electrodes are avoided with such configuration. | 11-14-2013 |
Patent application number | Description | Published |
20080219572 | METHOD AND APPARATUS FOR MOTION COMPENSATION SUPPORTING MULTICODEC - Provided are a method and apparatus for compensating motion of a moving image. The method includes calculating a pixel value of a pixel located between pixels of a reference image corresponding to a current image based on pixel values of the pixels of the reference image by using at least one method from among a plurality of methods, such as a vertical linear filtering, a horizontal linear filtering, and a cubic filtering, of interpolating the pixels of the reference image according to codec information indicating one of a plurality of codecs, such as MPEG4, H.264/AVC, and VC1, and restoring the current image by adding motion compensation data, including the calculated pixel value, and a difference between the reference image and the current image. | 09-11-2008 |
20090021648 | HISTOGRAM EQUALIZER AND HISTOGRAM EQUALIZATION METHOD - A histogram equalizer and histogram equalization method is provided. A histogram equalizer, including: a memory; and an operation unit which reads first data and second data from the memory, and then overwrites the second data of the memory with a summed value, the summed value being obtained by summing the read first data and the read second data. | 01-22-2009 |
20110283042 | Transaction splitting apparatus and method - A transaction splitting apparatus and method are provided in which neighboring sub-transactions accessing a predetermined bank in each memory may access different banks. The transaction splitting apparatus includes a first processing unit to split a transaction into at least one sub-transaction, the transaction accessing a first bank among a plurality of banks comprised in a memory, and a second processing unit to translate an address of the at least one sub-transaction, to interleave the at least one sub-transaction using the plurality of banks. | 11-17-2011 |
20120076432 | Median filtering method and apparatus - A median filtering apparatus and method for removing noise and improving an image quality with respect to all types of input images are provided. The median filtering apparatus may receive an input of N pieces of data, may form a data set including the N pieces of data, may calculate a difference array having an N×N size based on the N pieces of data in the data set, may sum component values for each column of the difference array, and may calculate an index of a column having a smallest value among sum values that are obtained by the summing operation and that are greater than or equal to a preset value. | 03-29-2012 |
20130315318 | DOUBLE REGISTER ARRAY BUFFER FOR MOTION COMPENSATION - Provided are a method and apparatus for buffering image data for motion compensation. One of two buffers of a double register array buffer, i.e., a first buffer, is selected as a buffer in which data corresponding to a row of a block of an image is to be written and the other of the double register array buffer is selected as a buffer from which data corresponding to another row of the block is to be read, thereby speeding up motion compensation processing when compared with the use of a single register array buffer. | 11-28-2013 |
20130343655 | APPARATUS AND METHOD EXTRACTING FEATURE INFORMATION OF A SOURCE IMAGE - Provided is an apparatus and method for extracting feature information of an image using a scale-invariant feature transform (SIFT) algorithm. The apparatus may include a first interface configured to generate one or more tile images from a first source image stored in a particular memory, such as a high-capacity short-term memory, and a feature information extractor configured to receive the generated one or more tile images and to respectively extract feature information from each of the one or more input tile images, where the first interface may be configured to generate the one or more tile images by selectively dividing the first source image into the one or more tile images based on a horizontal resolution of the first source image. | 12-26-2013 |
20140029851 | APPARATUS AND METHOD FOR CALCULATING CUMULATIVE HISTOGRAM OF IMAGE - An apparatus and method for calculating a cumulative histogram of an image are provided. A cumulative histogram calculation apparatus may include a cumulative value selecting unit to select cumulative data obtained by accumulating input data, based on a number of combinations of the input data, and a loading unit to load the selected cumulative value in a corresponding bin of a histogram. | 01-30-2014 |
20140333801 | METHOD AND APPARATUS FOR PROCESSING IMAGE ACCORDING TO IMAGE CONDITIONS - An image processing apparatus and a method are provided. The image processing apparatus includes an accumulator for accumulating image data in which images are accumulated when the images are input from an image sensor, a memory for storing the pieces of image data that are output from the accumulator, and a processor for generating a final image using at least one image data from among the pieces of image data that are stored in the memory. | 11-13-2014 |
Patent application number | Description | Published |
20130008020 | REMOVAL APPARATUSES FOR SEMICONDUCTOR CHIPS AND METHODS OF REMOVING SEMICONDUCTOR CHIPS - A removal apparatus for a semiconductor chip may include a stage configured to support a board on which the semiconductor chip is mounted by bumps, a laser configured to irradiate a laser beam into the board over an area larger than the semiconductor chip, and a picker configured to cause the laser beam to penetrate the semiconductor chip locally and to separate the semiconductor chip from the board. A method of removing a semiconductor chip from a board may include loading the board, on which the semiconductor chip is mounted by bumps, on a stage; irradiating a laser beam into the semiconductor chip to melt the bumps and to separate the semiconductor chip from the board; continuously irradiating the laser beam into the board on which solder pillars, that are residues of the bumps, remain to melt the solder pillars; and removing the solder pillars. | 01-10-2013 |
20130292833 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a lower semiconductor package including at least one lower semiconductor chip, at least one upper semiconductor package mounted on the lower semiconductor package to include at least one upper semiconductor chip, a molding layer provided between the lower and upper semiconductor packages, and connection solder balls provided in the molding layer to electrically connect the lower and upper semiconductor packages to each other. Each of the connection solder balls may include a portion protruding upward from the molding layer, and there may be no gap between the connection solder balls and the molding layer. | 11-07-2013 |
20150035184 | SUBSTRATE MANUFACTURING FACILITY AND METHOD OF MANUFACTURING SUBSTRATE - A substrate manufacturing facility includes a lower molding plate and an upper molding plate. A resin supply tray provides resin powder to a top surface of the lower molding plate. The lower and upper molding plates may compress a substrate and the resin powder. The upper molding plate has multiple apertures. The apertures are densely formed on a front side of the upper molding plate. The front side of the upper molding plate contacts the substrate. The apertures have diameters smaller than diameters of the resin powder. The substrate manufacturing facility includes a vacuum pump, a ventilator, a conduit, a controller, and valves. The substrate manufacturing facility can adsorb a circuit board using adsorption pressure from the vacuum pump and clean residue from the upper molding using exhaustion pressure from the ventilator. | 02-05-2015 |
Patent application number | Description | Published |
20080311727 | METHOD OF CUTTING A WAFER - In a method of cutting a wafer, a supporting member is attached to an upper surface of the wafer on which semiconductor chips are formed. An opening is formed at a lower surface of the wafer along a scribe lane of the wafer. The lower surface of the wafer may be plasma-etched to reduce a thickness of the wafer. A tensile tape may be attached to the lower surface of the wafer. Here, the tensile tape includes sequentially stacked tensile films having different tensile modules. The supporting member is then removed. The tensile tape is cooled to increase the tensile modules between the tensile films. The tensile tape is tensed until the tensile films are cut using the tensile modules difference to separate the tensile tape from the semiconductor chips. Thus, the lower surface of the wafer may be plasma-etched without using an etching mask. | 12-18-2008 |
20080315408 | Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same - Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin groups, and the plurality of semiconductor chips may be classified into a plurality of chip groups, and the pads of the semiconductor chips of like chip groups may be connected to the leads of like pin groups. | 12-25-2008 |
20090200362 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE - In a lead-free solder, a semiconductor package and a method of manufacturing the semiconductor package, the lead-free solder includes about 3.5 percent by weight to about 6 percent by weight of silver, about 0.05 percent by weight to about 0.5 percent by weight of copper and a remainder of tin. The lead-free solder is employed in the semiconductor package. The lead-free solder has high impact resistance and high heat resistance to reduce failures of the semiconductor package. | 08-13-2009 |
20100071854 | APPARATUS AND METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE - An apparatus and a method of manufacturing a semiconductor package are provided. A die attaching process and/or a wire bonding process for first and second surfaces of a lead frame are sequentially performed inside one equipment. Thus, time required for a semiconductor packaging process decreases and yield is increased. | 03-25-2010 |
20110110062 | Stack-type semiconductor device having chips having different backside structure and electronic apparatus including the same - A stack-type semiconductor device including semiconductor chips having different backside structures and an electronic apparatus including the stack-type semiconductor device include: a base frame for a semiconductor device; a first semiconductor chip that is mounted on the base frame and has a bottom surface having a first surface roughness; and a second semiconductor chip that is mounted on the first semiconductor chip and has a bottom surface having a second surface roughness, wherein the second surface roughness is greater than the first surface roughness by 1.2 nm or more. The stack-type semiconductor device is manufactured to be thin while cracking of the first semiconductor chip is prevented. In addition, changes in data caused by charge loss resulting from diffusion of metal ions, which can occur when a stack-type semiconductor device is a memory device, is prevented. | 05-12-2011 |
20110136334 | METHOD OF FORMING AT LEAST ONE BONDING STRUCTURE - A method of forming at least one bonding structure may be provided. A ball may be formed on the front end of a wire outside a capillary. The capillary may be moved downwardly to form a preliminary compressed ball on a first pad using the ball. The capillary may be moved upwardly to form a neck portion on the preliminary compressed ball using the preliminary compressed ball and the wire. The capillary may be moved obliquely and downwardly to form a compressed ball. The capillary may extend the wire from the compressed ball to a second pad. | 06-09-2011 |
20110293903 | WAVE SOLDERING APPARATUS TO APPLY BUOYANCY, SOLDERING METHOD, AND METHOD OF FORMING SOLDER BUMPS FOR FLIP CHIPS ON A SUBSTRATE - The present general inventive concept includes a wave soldering apparatus, a soldering method using the wave soldering apparatus, and a method of forming a solder bump for a flip chip. The wave soldering apparatus includes a solder bath containing a molten solder. A nozzle is arranged in the solder bath so as to upwardly spout the molten solder toward a bottom surface of a substrate that passes an upper portion of the solder bath. A liquid that is separated from the molten solder is contained in a downstream area of the solder bath, and buoyancy is applied to the molten solder, which is adhered to the substrate, by the liquid. Since the amount of the molten solder adhered to the substrate is increased by the buoyancy, it is possible to form the solder bump to have a height sufficient to use it as a flip chip. | 12-01-2011 |
20110318887 | METHOD OF MOLDING SEMICONDUCTOR PACKAGE - A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding. | 12-29-2011 |
20130203220 | METHOD OF MOLDING SEMICONDUCTOR PACKAGE - A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding. | 08-08-2013 |
20140242752 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer. | 08-28-2014 |
Patent application number | Description | Published |
20130000140 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - Provided are an apparatus and method for treating a substrate, and more particularly, to an apparatus and method for treating a substrate using a supercritical fluid. The apparatus for treating a substrate includes a process chamber in which an organic solvent remaining on a substrate is dissolved using a fluid provided as a supercritical fluid to dry the substrate and a recycling unit in which the organic solvent is separated from the fluid discharged from the process chamber to recycle the fluid. | 01-03-2013 |
20130000144 | APPARATUS FOR TREATING SUBSTRATE AND METHOD FOR DISCHARGING SUPERCRITICAL FLUID - Provided are an apparatus for treating a substrate and a method for discharge a supercritical fluid, and more particularly, an apparatus for treating a substrate using a supercritical fluid and a method for discharging the supercritical fluid using the same. The apparatus for treating the substrate includes a container for providing a supercritical fluid, a vent line through which the supercritical fluid is discharged from the container, and a freezing prevention unit disposed in the vent line to prevent the supercritical fluid from being frozen. | 01-03-2013 |
20140290093 | RECYCLING UNIT AND SUBSTRATE TREATING APPARATUS - The substrate treating apparatus includes a drying chamber in which an organic solvent remaining on a substrate is dissolved by using a fluid, and a recycling unit including a separator for separating the organic solvent from the fluid discharged from the drying chamber to recycle the fluid. The separator includes a distiller in which a fluid containing an organic solvent having a first concentration is introduced, a heating unit heating a fluid containing an organic solvent having a second concentration discharged from the distiller, and supplying an evaporated fluid containing an organic solvent having a third concentration into the distiller, and a condensation unit liquefying a fluid containing an organic solvent having a fourth concentration discharged from the distiller. The organic solvent has the second concentration, the first concentration, the third concentration, and the fourth concentration which are successively lowered in concentration. | 10-02-2014 |
Patent application number | Description | Published |
20130075720 | OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR INCLUDING THE SAME, AND THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME - An oxide semiconductor includes a first material including at least one selected from the group consisting of zinc (Zn) and tin (Sn), and a second material, where a value acquired by subtracting an electronegativity difference value between the second material and oxygen (O) from the electronegativity difference value between the first material and oxygen (O) is less than about 1.3. | 03-28-2013 |
20130260497 | METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL - A method for manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes, forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate, first heat treating the substrate comprising the oxide semiconductor layer, forming a source electrode and a drain electrode on the oxide semiconductor layer, the source and drain electrodes facing each other, and forming a passivation layer on the source electrode and the drain electrode. The first heat treating is performed at more than 1 atmosphere and at most 50 or less atmospheres. | 10-03-2013 |
20130306965 | THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME - A thin film transistor includes: a gate electrode on a substrate; a source electrode; a drain electrode positioned in a same layer as the source electrode and facing the source electrode; an oxide semiconductor layer positioned between the gate electrode and the source electrode or drain electrode; and a gate insulating layer positioned between the gate electrode and the source electrode or drain electrode. The oxide semiconductor layer includes titanium oxide (TiOx) doped with niobium (Nb). | 11-21-2013 |
Patent application number | Description | Published |
20120104394 | DISPLAY DEVICE - A display device in which various embodiments can prevent a vertically-striped blur is disclosed. In one aspect, the display device includes first gate lines, second gate lines, data lines, dummy data lines, and a plurality of pixels. The first and second gate lines are extended in a first direction. The data lines and the dummy data lines are extended in a second direction intersecting the first direction. The pixels are defined by the intersection of a first gate line of the first gate lines and a first data line of the data lines. | 05-03-2012 |
20120104441 | METHOD OF MANUFACTURING COLOR FILTER SUBSTRATE, SEMI-TRANSMISSIVE LIQUID CRYSTAL DISPLAY USING THE SAME, AND MANUFACTURING METHOD THEREOF - A manufacturing method of a color filter substrate, a semi-transmissive LCD using the same, and a manufacturing method thereof are disclosed. In one embodiment, the manufacturing method of the color filter substrate includes preparing a first substrate which comprises a reflection region and a transmission region. Then, a color resist on the first substrate is formed. A mask, including a semi-transmission mask corresponding to the reflection region, is provided on the color resist. An exposure process is provided for the color resist with the mask to form a color filter layer on the first substrate. The color filter layer is formed by removing a portion of the color resist of the reflection region. | 05-03-2012 |
Patent application number | Description | Published |
20130066441 | PROGRAMMABLE LOGIC CONTROLLER DEVICE AND METHOD FOR CONTROLLING THE SAME - Provided are a PLC device and a method for controlling the same. The method includes: receiving input data from an external; storing the received input data in an input area of a data input/output unit; reading the input data from the input area of the data input/output unit in order to perform a calculation operation; storing output data, which is a result of the calculation operation, in an output area of the data input/output unit; and transmitting the output data in the output area of the data input/output unit to an output circuit. | 03-14-2013 |
20140139263 | DATA PROCESSING APPARATUS AND METHOD IN PLC SYSTEM - A programmable logic controller (PLC) system, and more particularly, a data processing apparatus and method in the PLC system are provided. In the data processing method in a programmable logic controller (PLC) system, first dummy code data is output to an area having a chip selection signal for valid data output. The valid data is output after the first dummy code data is output. And second dummy code data is output when the valid data output is completed. | 05-22-2014 |
20150066168 | APPARATUS AND METHOD FOR UPDATING OPERATING SYSTEM IN PROGRAMMABLE LOGIC CONTROLLER - The present disclosure relates to an apparatus for updating an OS (Operating System) in PLC (Programmable Logic Controller) configured to update an OS in a PLC, and to perform an operation by instantly applying the updated OS to the PLC, and a method using the same, the apparatus including an MPU (Micro Processing Unit), a flash memory, a second working memory, and a switching unit. | 03-05-2015 |
Patent application number | Description | Published |
20100075256 | Onium salt compound, polymer compound comprising the salt compound, chemically amplified resist composition comprising the polymer compound, and method for patterning using the composition - A compound represented by the following formula (1) is provided: | 03-25-2010 |
20100112749 | POLYSILAZANE, METHOD OF SYNTHESIZING POLYSILAZANE, COMPOSITION FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE COMPOSITION - Disclosed are polysilazane, a method of synthesizing the polysilazane, a composition for manufacturing a semiconductor device, and a method of manufacturing a semiconductor device using the composition. The polysilazane is synthesized through a reaction, under a catalyst, between dichlorosilane, trichlorosilane, and ammonia added in a reaction solvent as a reactant. In this instance, a polystyrene conversion weight average molecular weight of the polysilazane is about 2,000 to 30,000. | 05-06-2010 |
20110201528 | Methods Of Forming An Oligomer Array - The present invention provides compositions for forming an oligomer array and methods for using the same. Such a composition may include an acid stable polymer, a photoacid generator and an organic solvent and may allow for the selective attachment of oligormers at one or more desired positions on a substrate using long wavelength light. | 08-18-2011 |
Patent application number | Description | Published |
20120099023 | DISPLAY DEVICE AND SYSTEM FOR WIRELESSLY TRANSMITTING/RECEIVING IMAGE SIGNALS - A display device and a system for wirelessly transmitting/receiving an image signal are provided. The display device includes: a display panel that displays an image; an upper housing that is disposed on a front surface of the display panel and has an open window defining a display area; a lower housing that is disposed on a rear surface of the display panel and has a hole formed in a portion of an area corresponding to the display area; and a wireless communication module that is disposed on a rear surface of the lower housing and transmits or receives a wireless signal through the hole. | 04-26-2012 |
20120127159 | METHOD OF DRIVING DISPLAY PANEL AND DISPLAY APPARATUS FOR PERFORMING THE SAME - A method of driving a display panel includes identifying a dimension of input data, where the input data is one of two-dimensional input data and three-dimensional input data, and generating first distributed data and second distributed data based on the dimension of the input data by at least one of copying the input data and dividing the input data into front data and back data. | 05-24-2012 |
20120206504 | COMPENSATION TABLE GENERATING SYSTEM, DISPLAY APPARATUS HAVING BRIGHTNESS COMPENSATION TABLE, AND METHOD OF GENERATING COMPENSATION TABLE - A compensation table generating system includes a test signal applying part which applies a test signal corresponding to reference gray scales to a display panel, an image obtaining part which obtains a test image of each of the reference gray scales displayed on the display panel based on the test signal, a position information extractor which measures a brightness distribution of each of the reference gray scales of the display panel based on the test image of each of the reference gray scales and extracts a representative position information of an stain area, in which a stain appears, based on the brightness distribution of each of the reference gray scales, a compensation data calculator which calculates a compensation data corresponding to a position of the stain area, and a brightness compensation table which stores the representative position information and the compensation data. | 08-16-2012 |
20130063428 | METHOD OF DISPLAYING AN IMAGE AND DISPLAY APPARATUS FOR PERFORMING THE SAME - A method of displaying an image, the method includes providing a source data frame and at least one copy data frame repeating the source data frame to a display panel and, selectively providing boosted light of a first luminance level to the display panel during a first period and normal light of a second luminance level to the display panel during a second period, based on the source data frame and the copy data frame, the second luminance level being smaller than the first luminance level, the second period being longer than the first period. | 03-14-2013 |
Patent application number | Description | Published |
20130093080 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes. | 04-18-2013 |
20150031149 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes. | 01-29-2015 |
Patent application number | Description | Published |
20130178016 | METHODS OF FABRICATING A PACKAGE-ON-PACKAGE DEVICE AND PACKAGE-ON-PACKAGE DEVICES FABRICATED BY THE SAME - Methods of fabricating a package-on-package device and package-on-package devices fabricated by the same may be provided. According to inventive concepts, a back-grinding of a semiconductor chip to a target thickness may be performed after the semiconductor chip is molded by a molding layer. Accordingly, the semiconductor chip is relatively thick while forming a molding layer, and thus less susceptible to a warpage phenomenon, which for instance may occur during the forming a molding layer. Thus, relatively thin package-on-package device, which is less susceptible to the warpage phenomenon, may be achieved. | 07-11-2013 |
20130270685 | PACKAGE-ON-PACKAGE ELECTRONIC DEVICES INCLUDING SEALING LAYERS AND RELATED METHODS OF FORMING THE SAME - A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer. | 10-17-2013 |
20140008818 | METHOD AND APPARATUS FOR STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip. | 01-09-2014 |
20140151863 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package includes a wiring board, a semiconductor chip mounted on the wiring board, and a mounting connection terminal electrically connecting a bonding pad of the semiconductor chip to a first connection pad of the wiring board. The mounting connection terminal includes a core portion and a connecting shell solder portion substantially surrounding the core portion. The core portion of the mounting connection terminal is not in contact with the bonding pad of the semiconductor chip. | 06-05-2014 |
20140273348 | PACKAGE-ON-PACKAGE ELECTRONIC DEVICES INCLUDING SEALING LAYERS AND RELATED METHODS OF FORMING THE SAME - A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer. | 09-18-2014 |
20140374883 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region. | 12-25-2014 |
20150031170 | METHOD AND APPARATUS FOR STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip. | 01-29-2015 |
Patent application number | Description | Published |
20130276983 | INJECTION MEMBER FOR MANUFACTURING SEMICONDUCTOR DEVICE AND PLASMA PROCESSING APPARATUS HAVING THE SAME - A plasma processing apparatus may include a process chamber configured to perform a plasma using process and contain a plurality of substrates, a support member provided in the process chamber, the substrates being laid on the same level of the support member, an injection member provided to face the support member and include a plurality of baffles, such that at least one reaction gas and a purge gas can be injected onto the substrates in an independent manner, and a driving part configured to rotate the support member or the injection member, such that the baffles of the injection member can orbit with respect to the plurality of the substrates laid on the support member. The injection member may include a plasma generator, which may be provided on at least one, configured to inject the reaction gas, of the baffles to turn the reaction gas into plasma. | 10-24-2013 |
20140193967 | METHOD OF FORMING AN EPITAXIAL LAYER ON A SUBSTRATE, AND APPARATUS AND SYSTEM FOR PERFORMING THE SAME - In a method of forming an epitaxial layer, an etching gas may be decomposed to form decomposed etching gases. A source gas may be decomposed to form decomposed source gases. The decomposed source gases may be applied to a substrate to form the epitaxial layer on the substrate. A portion of the epitaxial layer on a specific region of the substrate may be etched using the decomposed etching gases. Before the etching gas is introduced into the reaction chamber, the etching gas may be previously decomposed. The decomposed etching gases may then be introduced into the reaction chamber to etch the epitaxial layer on the substrate. As a result, the epitaxial layer on the substrate may have a uniform distribution. | 07-10-2014 |