Patent application number | Description | Published |
20080241757 | Reproducible, high yield method for fabricating ultra-short T-gates on HFETs - A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer. | 10-02-2008 |
20100163936 | Structure and Method for Fabrication of Field Effect Transistor Gates With or Without Field Plates - A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate. | 07-01-2010 |
20100301395 | Asymmetrically recessed high-power and high-gain ultra-short gate HEMT device - A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device. | 12-02-2010 |
20120205726 | Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates - A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate. | 08-16-2012 |
20120208359 | Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates - A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate. | 08-16-2012 |
20130230951 | ASYMMETRICALLY RECESSED HIGH-POWER AND HIGH-GAIN ULTRA-SHORT GATE HEMT DEVICE - A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device. | 09-05-2013 |
20130295757 | SHORT GATE-LENGTH HIGH ELECTRON-MOBILITY TRANSISTORS WITH ASYMMETRIC RECESS AND SELF-ALIGNED OHMIC ELECTRODES - A method for fabricating InP-based high electron-mobility transistors (HEMTs) and GaAs-based metamorphic electron-mobility transistors (MHEMTs) by utilizing asymmetrically recessed Γ-gates and self-aligned ohmic electrodes is disclosed. The fabrication starts with mesa isolation, followed by gate recess and gate metal deposition, in which the gate foot is placed asymmetrically in the recess groove, with the offset towards the source. It is important to use Γ-gates as the shadow mask for ohmic metal deposition, because it allows a source-gate spacing as small as 0.1 micron, greatly reducing the critical source resistance, and it retains a relatively large gate-drain spacing, enabling a decent breakdown voltage when coupled with the asymmetric gate recess. It is also critical to maintain a large stem height of the Γ-gates to assure a sufficient gap between the top of the gates and the ohmic metal after its deposition to reduce the parasitic capacitance. The uniqueness of this technology would best fit the applications that require low voltage and/or low DC power consumption. | 11-07-2013 |
20130341644 | METHOD AND DESIGN OF AN RF THRU-VIA INTERCONNECT - In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink. | 12-26-2013 |