Patent application number | Description | Published |
20090179310 | Pillar devices and methods of making thereof - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings. | 07-16-2009 |
20090258489 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same - A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode. | 10-15-2009 |
20100327254 | Methods to improve electrode diffusions in two-terminal non-volatile memory devices - A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality of pillars is rounded. A method of making non-volatile memory device includes forming a stack of device layers, and patterning the stack to form a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell that contains a steering element and a storage element, and where at least one of top corner or bottom corner of each of the plurality of pillars is rounded. | 12-30-2010 |
20110136326 | PILLAR DEVICES AND METHODS OF MAKING THEREOF - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings. | 06-09-2011 |
Patent application number | Description | Published |
20150117813 | Mode Size Adjusting For Edge Coupling Devices - An apparatus comprising a waveguide along a longitudinal axis at a first elevation, an optical splitter coupled to a first edge of the waveguide along the longitudinal axis, two or more inverse tapers coupled to a second edge of the optical splitter along the longitudinal axis, and one or more offset inverse tapers that are substantially parallel with the two or more inverse tapers, wherein the one or more offset inverse tapers are along the longitudinal axis at a second elevation. | 04-30-2015 |
20150285997 | Edge Coupling Using Adiabatically Tapered Waveguides - An apparatus comprising a thick waveguide comprising a first adiabatic tapering from a first location to a second location, wherein the first adiabatic tapering is wider at the first location than at the second location, and a thin slab waveguide comprising a second adiabatic tapering from the first location to the second location, wherein the second adiabatic tapering is wider at the second location than at the first location, and a third adiabatic tapering from the second location to a third location, wherein the third adiabatic tapering is wider at the second location than at the third location, wherein at least a portion of the first adiabatic tapering is adjacent to the second adiabatic tapering, and wherein the first adiabatic tapering and the second adiabatic tapering are separated from each other by a constant gap. | 10-08-2015 |
20150293303 | Edge Coupling Device Fabrication - A method of fabricating an edge coupling device and an edge coupling device are provided. The method includes removing a portion of cladding material to form a trench over an inversely tapered silicon waveguide, depositing a material having a refractive index greater than silicon dioxide over remaining portions of the cladding material and in the trench, and removing a portion of the material within the trench to form a ridge waveguide. | 10-15-2015 |
20150316720 | Inverse Taper Waveguides for Low-Loss Mode Converters - An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide (SiO2) layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer. | 11-05-2015 |
Patent application number | Description | Published |
20090065814 | MOS device with schottky barrier controlling layer - A semiconductor device is formed on a semiconductor substrate. The semiconductor device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and the body into the drain, an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain form a Schottky diode, and a Schottky barrier controlling layer disposed in the epitaxial layer adjacent to the active region contact trench. | 03-12-2009 |
20090065855 | MOS device with integrated schottky diode in active region contact trench - A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and at least part of the body into the drain, wherein the active region contact trench is shallower than the body bottom surface, and an active region contact electrode disposed within the active region contact trench. | 03-12-2009 |
20090065861 | MOS device with low injection diode - A semiconductor device is formed on a semiconductor substrate. The device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and into the body, an active region contact electrode disposed within the active region contact trench, wherein a thin layer of body region separating the active region contact electrode from the drain. | 03-12-2009 |
20110042727 | MOSFET device with reduced breakdown voltage - A semiconductor device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, a contact trench extending through the source and at least part of the body, a contact electrode disposed in the contact trench, and an epitaxial enhancement portion disposed below the contact trench, wherein the epitaxial enhancement portion has the same carrier type as the epitaxial layer. | 02-24-2011 |
20120068262 | Integrated MOSFET Device and Method with Reduced Kelvin Contact Impedance and Breakdown Voltage - A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed. | 03-22-2012 |
20120080751 | MOS DEVICE WITH VARYING CONTACT TRENCH LENGTHS - A semiconductor device is formed on a semiconductor substrate. The device comprises a drain; an epitaxial layer overlaying the drain; a body disposed in the epitaxial layer, having a body top surface and a body bottom surface; a source embedded in the body, extending from the body top surface into the body; a first gate trench extending into the epitaxial layer; a first gate disposed in the first gate trench; an active region contact trench extending through the source and at least part of the body into the drain; an active region contact electrode disposed within the active region contact trench; a second gate trench extending into the epitaxial layer; a second gate disposed in the gate trench; a gate contact trench formed within the second gate; and a gate contact electrode disposed within the gate contact trench. | 04-05-2012 |
20130001683 | FLEXIBLE CRSS ADJUSTMENT IN A SGT MOSFET TO SMOOTH WAVEFORMS AND TO AVOID EMI IN DC-DC APPLICATION - A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device. | 01-03-2013 |
20130009242 | MOS DEVICE WITH LOW INJECTION DIODE - A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction. | 01-10-2013 |
20130015550 | JUNCTION BARRIER SCHOTTKY DIODE WITH ENFORCED UPPER CONTACT STRUCTURE AND METHOD FOR ROBUST PACKAGINGAANM Bhalla; AnupAACI Santa ClaraAAST CAAACO USAAGP Bhalla; Anup Santa Clara CA USAANM Pan; JiAACI San JoseAAST CAAACO USAAGP Pan; Ji San Jose CA USAANM Ng; DanielAACI CampbellAAST CAAACO USAAGP Ng; Daniel Campbell CA US - A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode. | 01-17-2013 |
20130200451 | NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT - A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region. | 08-08-2013 |
20130203224 | FABRICATION OF MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; forming a body contact implant on a sidewall of the contact trench; forming a diode enhancement layer along bottom of the contact trench, the diode enhancement layer having opposite carrier type as the epitaxial layer; disposing an epitaxial enhancement portion below the diode enhancement layer, the epitaxial enhancement portion having the same carrier type as the epitaxial layer; and disposing a contact electrode in the contact trench; wherein: a distance between top surface of the substrate and bottom of the epitaxial enhancement layer is shorter than a distance between the top surface of the substrate and bottom of the body. | 08-08-2013 |
20130203225 | FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into the drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. | 08-08-2013 |
20130280870 | FABRICATION OF MOS DEVICE WITH INTEGRATED SCHOTTKY DIODE IN ACTIVE REGION CONTACT TRENCH - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer, having a body top surface and a body bottom surface; forming a source; forming an active region contact trench that extends through the source and the body into the drain, wherein bottom surface of the active region contact trench is formed to include at least a portion that is shallower than the body bottom surface; and disposing a contact electrode within the active region contact trench. | 10-24-2013 |
20130334599 | INTEGRATED SNUBBER IN A SINGLE POLY MOSFET - A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more electrical connections between the snubber electrode and portions of the body region and a source electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 12-19-2013 |
20140054687 | MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE - A semiconductor device includes a drain region, an epitaxial layer overlaying the drain region, and an active region. The active region includes: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; a contact trench extending through the source and at least part of the body; a contact electrode disposed in the contact trench; and an implant disposed at least in part along a contact trench wall; and an epitaxial enhancement portion disposed below the contact trench and in contact with the implant. | 02-27-2014 |
20140179074 | METHOD OF MAKING MOSFET INTEGRATED WITH SCHOTTKY DIODE WITH SIMPLIFIED ONE-TIME TOP-CONTACT TRENCH ETCHING - Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)06-26-2014 | |
20140235024 | Method of Making MOSFET Integrated with Schottky Diode with Simplified One-time Top-Contact Trench Etching - Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)08-21-2014 | |
20140239388 | TERMINATION TRENCH FOR POWER MOSFET APPLICATIONS - Aspects of the present disclosure describe a termination structure for a power MOSFET device. A termination trench may be formed into a semiconductor material and may encircle an active area of the MOSFET. The termination trench may comprise a first and second portion of conductive material. The first and second portions of conductive material are electrically isolated from each other. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 08-28-2014 |
20140252494 | INTEGRATED SNUBBER IN A SINGLE POLY MOSFET - Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 09-11-2014 |
20140319605 | NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT - A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region. | 10-30-2014 |
20140357030 | FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The Schottky barrier controlling layer controls Schottky barrier height of a Schottky diode formed by the contact electrode and the drain. | 12-04-2014 |
20150333174 | SEMICONDUCTOR DEVICE WITH TERMINATION STRUCTURE FOR POWER MOSFET APPLICATIONS - A semiconductor device may have an active device region containing a plurality of active devices and a termination structure that surrounds the active device region. The termination structure includes a first conductive region that surrounds the active device region, an insulator region that surrounds the first conductive region, and a second conductive region that surrounds the first conductive region and the insulator region. The active device region and termination structure are formed into a semiconductor material of a first conductivity type. The first conductive region is electrically connected to a gate metal and the second conductive region is connected to a drain metal. | 11-19-2015 |
Patent application number | Description | Published |
20090153258 | MEMS resonator array structure and method of operating and using same - Each one of resonators arranged in an N×M MEMS array structure includes substantially straight elongated beam sections connected by curved/rounded sections and is mechanically coupled to at least one adjacent resonator of the array via a coupling section, each elongated beam section connected to another elongated beam section at a distal end via the curved/rounded sections forming a geometric shape (e.g., a rounded square), and the coupling sections disposed between elongated beam sections of adjacent resonators. The resonators, when induced, oscillate at substantially the same frequency, in combined elongating/breathing and bending modes, i.e., beam sections exhibiting elongating/breathing-like and bending-like motions. One or more of the array structure's resonators may include one or more nodal points (i.e., that are substantially stationary and/or experience little movement), which are suitable and/or preferable locations to anchor the resonator/array to the substrate, in one or more areas of the structure's curved sections. | 06-18-2009 |
20090153267 | MEMS resonator structure and method - A microelectromechanical resonator may include one or more resonator masses that oscillates in a bulk mode and that includes a first plurality of regions each having a density, and a second plurality of regions each having a density, the density of each of the second plurality of regions differing from the density of each of the first plurality of regions. The second plurality of regions may be disposed in a non-uniform arrangement. The oscillation may include a first state in which the resonator mass is contracted, at least in part, in a first and/or a second direction, and expanded, at least in part, in a third and/or a fourth direction, the second direction being opposite the first direction, the fourth direction being opposite the third direction. | 06-18-2009 |
20100263447 | TRI-AXIS ACCELEROMETER HAVING A SINGLE PROOF MASS AND FULLY DIFFERENTIAL OUTPUT SIGNALS - A tri-axis accelerometer includes a proof mass, at least four anchor points arranged in at least two opposite pairs, a first pair of anchor points being arranged opposite one another along a first axis, a second pair of anchor points being arranged opposite one another along a second axis, the first axis and the second axis being perpendicular to one another, and at least four spring units to connect the proof mass to the at least four anchor points, the spring units each including a pair of identical springs, each spring including a sensing unit. | 10-21-2010 |
20110018655 | MEMS RESONATOR STRUCTURE AND METHOD - A microelectromechanical resonator may include one or more resonator masses that oscillates in a bulk mode and that includes a first plurality of regions each having a density, and a second plurality of regions each having a density, the density of each of the second plurality of regions differing from the density of each of the first plurality of regions. The second plurality of regions may be disposed in a non-uniform arrangement. The oscillation may include a first state in which the resonator mass is contracted, at least in part, in a first and/or a second direction, and expanded, at least in part, in a third and/or a fourth direction, the second direction being opposite the first direction, the fourth direction being opposite the third direction. | 01-27-2011 |
20110199167 | MEMS RESONATOR ARRAY STRUCTURE AND METHOD OF OPERATING AND USING SAME - Each one of resonators arranged in an N×M MEMS array structure includes substantially straight elongated beam sections connected by curved/rounded sections and is mechanically coupled to at least one adjacent resonator of the array via a coupling section, each elongated beam section connected to another elongated beam section at a distal end via the curved/rounded sections forming a geometric shape (e.g., a rounded square), and the coupling sections disposed between elongated beam sections of adjacent resonators. The resonators, when induced, oscillate at substantially the same frequency, in combined elongating/breathing and bending modes, i.e., beam sections exhibiting elongating/breathing-like and bending-like motions. One or more of the array structure's resonators may include one or more nodal points (i.e., that are substantially stationary and/or experience little movement), which are suitable and/or preferable locations to anchor the resonator/array to the substrate, in one or more areas of the structure's curved sections. | 08-18-2011 |