Patent application number | Description | Published |
20100093288 | METHOD AND APPARATUS FOR FACILITATING POWER CONSERVATION VIA TIME-GATING IN A WIRELESS COMMUNICATION SYSTEM - The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal. | 04-15-2010 |
20100167685 | DISCRETE TIME RECEIVER - A discrete time receiver includes a low noise transconductance amplifier (LNTA), a discrete time sampler, a passive discrete time circuit, and a switched capacitor amplifier. The LNTA amplifies a received RF signal and provides an amplified RF signal. The discrete time sampler samples the amplified RF signal (e.g., with multiple phases of a sampling clock) and provides first analog samples. The passive discrete time circuit decimates and filters the first analog samples and provides second analog samples. The switched capacitor amplifier amplifies the second analog samples and provides third analog samples. The discrete time receiver may further include a second passive discrete time circuit, a second switched capacitor amplifier, and an analog-to-digital converter (ADC) that digitizes baseband analog samples and provides digital samples. The discrete time receiver can flexibly support different system bandwidths and center frequencies. | 07-01-2010 |
20100198898 | PASSIVE SWITCHED-CAPACITOR FILTERS CONFORMING TO POWER CONSTRAINT - Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner. | 08-05-2010 |
20100225419 | PASSIVE SWITCHED-CAPACITOR FILTERS - A passive switched-capacitor (PSC) filter includes (i) an array of capacitors that can store and share electrical charge and (ii) an array of switches that can couple the capacitors to a summing node. Each switch couples an associated capacitor to the summing node when enabled. Each capacitor stores a voltage value from the summing node when selected for charging and shares electrical charge with other capacitors via the summing node when selected for charge sharing. The PSC filter may include multiple sections for multiple filter taps. Each section includes one or more capacitors of equal size determined based on a corresponding filter coefficient. The capacitors in each section may be sequentially selected for charging with an input or output signal, one capacitor in each clock cycle. In each clock cycle, one capacitor in each section may be selected for charge sharing to generate the output signal. | 09-09-2010 |
20100237710 | PASSIVE DIFFERENTIAL VOLTAGE DOUBLER - Techniques for generating a differential output voltage between first and second output voltages that is double a differential input voltage between first and second input voltages. In one aspect, first and second capacitors of a constituent voltage doubler are charged to a differential input voltage during a charging phase. During an output phase non-overlapping in time with the charging phase, the first and second capacitors are stacked in series to generate the differential output voltage. The first and second capacitors are both coupled to a single common-mode voltage to provide a predefined common-mode output voltage. Further techniques for providing two or more constituent voltage doublers to extend the output phase are described. | 09-23-2010 |
20120044927 | RADIO CHANNEL AGGREGATION AND SEGMENTATION - Multiple streams from multiple circuit paths are Block-TDM (Block-Time-Division-Multiplexing) aggregated into a single stream that passes via a single path through processing circuitry capable of handling the aggregated signal. The cost of providing redundant processing circuitry is avoided. After processing in the single path, the resulting signal is Block-TDM de-aggregated to generate multiple streams. Each output stream is substantially the same as if its corresponding input stream had been processed in a separate path using separate processing circuitry. The path-sharing technique is usable to pass multiple streams from multiple radio receivers through one superior Delta-Sigma ADC (DSADC) as opposed to using multiple flat ADCs to process information from the multiple receivers. In one example, the DSADC can be used because the aggregation is Block-TDM-based and the de-aggregator involves a digital low pass filter. In another example, the de-aggregator involves a decoder and the aggregator involves a precoder. | 02-23-2012 |
20130245999 | SPIN TORQUE TRANSFER MAGNETIC TUNNEL JUNCTION INTELLIGENT SENSING - Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics. | 09-19-2013 |
20140082038 | Passive switched-capacitor filters conforming to power constraint - Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner. | 03-20-2014 |
20140082040 | Passive switched-capacitor filters conforming to power constraint - Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner. | 03-20-2014 |
20140254448 | METHOD AND APPARATUS FOR FACILITATING POWER CONSERVATION VIA TIME-GATING IN A WIRELESS COMMUNICATION SYSTEM - The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal. | 09-11-2014 |
Patent application number | Description | Published |
20150237583 | CURRENT-EFFICIENT LOW NOISE AMPLIFIER (LNA) - A device includes a multi-mode low noise amplifier (LNA) having a first amplifier stage, and a second amplifier stage coupled to the first amplifier stage, the second amplifier stage having a plurality of amplification paths configured to amplify a plurality of carrier frequencies, the first amplifier stage configured to bypass the second amplifier stage when the first amplifier stage is configured to amplify a single carrier frequency. | 08-20-2015 |
20150333761 | VCO-COUPLING MITIGATION IN A MULTIPLE-CARRIER, CARRIER AGGREGATION RECEIVER - Aspects of a wireless apparatus for configuring a plurality of VCOs are provided. The apparatus may be a UE. The UE receives a configuration for a plurality of carriers. Each carrier corresponds to a different LO frequency. In addition, the UE determines a VCO frequency for generating each LO frequency. Further, the UE assigns each determined VCO frequency to each of a plurality of VCO modules based on a distance between the VCO modules and each of the determined VCO frequencies. The plurality of VCO modules are of a set of VCO modules including at least three VCO modules. | 11-19-2015 |
20150333815 | MULTI-WAY DIVERSITY RECEIVER WITH MULTIPLE SYNTHESIZERS IN A CARRIER AGGREGATION TRANSCEIVER - Certain aspects of the present disclosure provide multi-way diversity receivers with multiple synthesizers. Such a multi-way diversity receiver may be implemented in a carrier aggregation (CA) transceiver. One example wireless reception diversity circuit generally includes three or more receive paths for processing received signals and two or more frequency synthesizing circuits configured to generate local oscillating signals to downconvert the received signals. Each of the frequency synthesizing circuits is shared by at most two of the receive paths, and each pair of the frequency synthesizing circuits may generate a pair of local oscillating signals having the same frequency. | 11-19-2015 |
20150333941 | RADIO FREQUENCY (RF) FRONT END HAVING MULTIPLE LOW NOISE AMPLIFIER MODULES - A radio frequency (RF) front end having multiple low noise amplifiers modules is disclosed. In an exemplary embodiment, an apparatus includes at least one first stage amplifier configured to amplify received carrier signals to generate at least one first stage carrier group. Each first stage carrier group includes a respective portion of the carrier signals. The apparatus also includes second stage amplifiers configured to amplify the first stage carrier groups. Each second stage amplifier configured to amplify a respective first stage carrier group to generate two second stage output signals that may be output to different demodulation stages where each demodulation stage demodulates a selected carrier signal. | 11-19-2015 |
20150333949 | MULTIPLEX MODULES FOR CARRIER AGGREGATION RECEIVERS - Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports. | 11-19-2015 |
20150334710 | DYNAMIC LOCAL OSCILLATOR (LO) SCHEME AND SWITCHABLE RECEIVE (RX) CHAIN FOR CARRIER AGGREGATION - Certain aspects of the present disclosure provide methods and apparatus for dynamically adjusting a voltage-controlled oscillator (VCO) frequency, a local oscillator (LO) divider ratio, and/or a receive path when adding or discontinuing reception of a component carrier (CC) in a carrier aggregation (CA) scheme. This dynamic adjustment is utilized to avoid (or at least reduce) VCO, LO, and transmit signal coupling issues with multiple component carriers, with minimal (or at least reduced) current consumption by the VCO and the LO divider. | 11-19-2015 |
20150334711 | Avoiding Spurious Responses with Reconfigurable LO Dividers - Methods and apparatus including: setting up a plurality of configurations for a plurality of local oscillator (LO) paths of a carrier aggregation (CA) transceiver operating with a plurality of bands; calculating and comparing frequencies for each LO path of the plurality of LO paths and at least one divider ratio of LO dividers for each band of the plurality of bands to identify frequency conflicts; and reconfiguring the LO dividers for the plurality of LO paths and the plurality of bands when the frequency conflicts are identified. | 11-19-2015 |
20150349722 | Dual Stage Carrier-Aggregation (CA) Low Noise Amplifier (LNA) Having Harmonic Rejection and High Linearity - A device includes a load circuit configured to receive an amplified communication signal, the load circuit having a center tapped inductor structure configured to divide the amplified communication signal into a first portion and a second portion, the load circuit configured to resonate at a harmonic of the amplified communication signal. | 12-03-2015 |
20150349724 | DISTORTION CANCELLATION FOR DUAL STAGE CARRIER-AGGREGATION (CA) LOW NOISE AMPLIFIER (LNA) NON-LINEAR SECOND ORDER PRODUCTS - A device includes a main two-stage low noise amplifier (LNA) configured to amplify a carrier aggregation (CA) communication signal, the main two-stage LNA comprising a first LNA stage and a second LNA stage, an output of the first LNA stage having a first stage second order intermodulation product, the second LNA stage comprising a phase-inverter configured to phase-invert the output of the first LNA stage to generate a second stage phase-inverted output, and an auxiliary LNA stage coupled to the main two-stage LNA, the auxiliary LNA stage configured to cancel the first stage second order intermodulation product. | 12-03-2015 |
20150349907 | Reconfigurable Multi-Mode Transceiver - Reconfiguring a transceiver design using a plurality of frequency synthesizers and a plurality of carrier aggregation (CA) receiver (Rx) and transmitter (Tx) chains, the method including: connecting a first frequency synthesizer to a first CA Tx chain; connecting the plurality of frequency synthesizers to the plurality of CA Rx chains, wherein a second frequency synthesizer of the plurality of frequency synthesizers is connected as a shared synthesizer to a first CA Rx chain and a second CA Tx chain. | 12-03-2015 |
20160087587 | DUAL STAGE LOW NOISE AMPLIFIER FOR MULTIBAND RECEIVER - A dual stage LNA for use in multiband receivers is disclosed. In an exemplary embodiment, an apparatus includes a plurality of first stage amplifiers having a plurality of first stage output ports, respectively, to output first stage amplified voltage mode signals. The apparatus also includes a plurality of second stage amplifiers having a plurality of second stage input ports, respectively, and second stage output ports to output amplified current mode signals. The apparatus also includes a switch apparatus having input terminals connected to the first stage output ports and output terminals connected to the second stage input ports, the switch apparatus to connect selected second stage input ports to selected first stage output ports. | 03-24-2016 |
Patent application number | Description | Published |
20090124204 | Minimum Finger Low-Power Demodulator For Wireless Communication - Techniques for assigning multipaths to finger processors to achieve the desired data performance and low power consumption are described. A search is initially performed to obtain a set of multipaths for a transmission from at least one base station. At least one multipath (e.g., the minimum number of multipaths) having a combined performance metric (e.g., a combined SNR) exceeding a threshold is identified. The at least one multipath is assigned to, and processed by, at least one finger processor to recover the transmission from the base station(s). | 05-14-2009 |
20100183096 | EFFICIENT MULTI-SYMBOL DEINTERLEAVER - Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power. | 07-22-2010 |
20110075615 | RECURSIVE REALIZATION OF POLYNOMIAL PERMUTATION INTERLEAVING - Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance. | 03-31-2011 |
20110107019 | APP (A PRIORI PROBABILITY) STORAGE DESIGN FOR LTE TURBO DECODER WITH QUADRATIC PERMUTATION POLYNOMIAL INTERLEAVER - Systems and methodologies are described that facilitate ensuring contention and/or collision free memory within a turbo decoder. A Posteriori Probability (APP) Random Access Memory (RAM) can be segmented or partitioned into two or more files with an interleaving sub-group within each file. This enables parallel operation in a turbo decoder and allows a turbo decoder to access multiple files simultaneously without memory access contention. | 05-05-2011 |
20110143672 | METHOD AND SYSTEMS FOR PARALLEL CHANNEL ESTIMATION AND INTERFERENCE CANCELLATION - Certain aspects of the disclosure propose parallel channel estimation and interference cancellation in a wireless communications system. For each common reference signal tone offset, interference cancellation and channel estimation may be performed independently. The proposed channel estimation method may increase performance of a system. | 06-16-2011 |
20110194430 | METHOD AND APPARATUS FOR UNIFIED CHANNEL ESTIMATION FOR WIRELESS COMMUNICATION - Certain aspects of the disclosure propose a unified channel estimation algorithm that combines two or more channel estimation algorithms in a single piece of hardware or software. The proposed unified channel estimation may dynamically switch, based on one or more metrics, between different modes of operation that utilize different channel estimation algorithms. | 08-11-2011 |
20110249548 | EFFICIENT ZADOFF-CHU SEQUENCE GENERATION - Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters. | 10-13-2011 |
20110280133 | SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING - Certain aspects of the present disclosure relate to a method for processing wireless communications. According to one aspect, a processing unit may receive a plurality of code blocks of a transport block and schedule the plurality of code blocks to be decoded in parallel with a plurality of decoders. Each decoder decodes at least one code block as an independent tasks. The processing unit further collects the decoded information bits from the plurality of decoders and forwards the collected decoded information bits for further processing. In one aspect, the processing unit includes an output agent to temporarily store the decoded information bits while waiting for all code blocks of the transport block to be decoded. | 11-17-2011 |
20110280185 | METHOD AND APPARATUS FOR PARALLEL DE-INTERLEAVING OF LTE INTERLEAVED DATA - A wireless communication signal in Long Term Evolution (LTE) may be interleaved in a manner which permits a partitioning of a received inter-column bit-reversed interleaved code block for improved de-interleaving. The code block may be divided into equal subportions which may be simultaneously de-interleaved both forward and backward, and in parallel with other subportions. An even number of subportions may be provided. Dividing a received code block in this manner may improve de-interleaving performance. | 11-17-2011 |
Patent application number | Description | Published |
20150035839 | SYSTEM AND METHOD FOR PROVIDING POSITIVE AND NEGATIVE VOLTAGES WITH A SINGLE INDUCTOR - This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for providing positive and negative voltages using a single inductor. In one aspect, the apparatus includes a single inductor having a first end and a second end. The first end is coupled to a first switch and configured to connect to either a power source or a negative output node depending on the state of the first switch. The second end is coupled to a second switch and is configured to connect to either a ground potential or a positive output node depending on the state of the second switch. The apparatus further includes a controller adapted to configure the switches into one of a plurality of configurations at a time. | 02-05-2015 |
20150194083 | ADAPTIVE POWER-EFFICIENT HIGH-SPEED DATA LINK BETWEEN DISPLAY CONTROLLER AND COMPONENT ON GLASS DRIVER ICS - This disclosure provides systems, methods and apparatus for a display device incorporating high-speed data links. A display device can include a controller and a plurality of driver integrated circuits (ICs) for driving portions of a display panel. The controller can communicate data and control signals with the plurality of driver ICs over a plurality of links. The controller can adjust power consumed for communication over one link independently of the power consumed for communication over other links. The controller can adjust power consumed by the controller and a driver IC, as well as transmitter and receiver parameters to provide an acceptable quality of data transmission over the corresponding link. The controller can adjust the power consumed by adjusting a voltage swing of one or more transmission amplifiers and/or controlling the current supplied to receiver amplifiers of the driver ICs. | 07-09-2015 |
20160035314 | DISPLAY WITH FIELD SEQUENTIAL COLOR (FSC) FOR OPTICAL COMMUNICATION - This disclosure provides systems, methods and apparatus for providing displays. In one aspect, a display has an optical data path for transmitting data between a controller and an array of display elements. The controller couples to a transmitter for transmitting an optical signal and the display elements couple to a receiver that receives optical signals. The transmitter transmits an optical signal that carries control data for controlling the operation of the display element. The receiver receives the control data and provides the control data to a driver that uses the control data to control the operation of the display element. In some implementations, the control data is multiplexed with image data and communication data to provide an optical data path that carries image data and control data for forming an image and that carries communication data that can propagate through the display and to a remote location. | 02-04-2016 |
20160078842 | UNIVERSAL DIGITAL CONTROLLER DESIGN FOR DC/DC SWITCHING POWER SUPPLIES USED IN DISPLAYS - This disclosure provides systems, methods and apparatus for a power supply module capable of providing power to a display apparatus. In one aspect, the power supply module can include a power supply controller that is capable executing commutation cycles, where each commutation cycle includes energizing an inductor for a first time period and then allowing the energized inductor to supply power to the display apparatus for a second time period. The power supply module can operate in active-high and active-low states, in which the power supply module executes commutation cycles, and a suspend state, in which no commutation cycles are executed. The power supply module transitions between these states based in part on the value of the output voltage. A peak current value is varied such that that the power supply module converges to operating in the active-high and active-low states after peak current demand is met. | 03-17-2016 |
Patent application number | Description | Published |
20140205140 | SYSTEMS, DEVICES, AND METHODS FOR TRACKING MOVING TARGETS - A system for tracking a moving target having up to six degrees of freedom and rapidly determining positions of the target, said system includes an easy to locate precision optical target fixed to the target. This system includes at least two cameras positioned so as to view the optical camera from different directions with each of the at least two cameras being adapted to record two dimensional images of the precision optical target defining precise target point. A computer processor is programmed to determine the target position of x, y and z and pitch, roll and yaw. In an embodiment, the system can be configured to utilize an iteration procedure whereby an approximate first-order solution is proposed and tested against the identified precise target points to determine residual errors which can be divided by the local derivatives with respect to each component of rotation and translation, to determine an iterative correction. | 07-24-2014 |
20160035108 | SYSTEMS, DEVICES, AND METHODS FOR TRACKING AND COMPENSATING FOR PATIENT MOTION DURING A MEDICAL IMAGING SCAN - A motion tracking system for dynamic tracking of and compensation for motion of a patient during a magnetic resonance scan comprises a first camera positioned to view an optical marker along a first line of sight; a second camera positioned to view the optical marker along a second line of sight; and a computer system configured to analyze images generated by the first and second cameras to determine changes in position of the optical marker, and to generate tracking data for use by a magnetic resonance scanner to dynamically adjust scans to compensate for the changes in position of the optical marker, wherein the computer system is configured to dynamically adapt its image analysis to utilize images from all cameras that are currently viewing the optical marker. | 02-04-2016 |
20160073962 | SYSTEMS, DEVICES, AND METHODS FOR TRACKING AND COMPENSATING FOR PATIENT MOTION DURING A MEDICAL IMAGING SCAN - A motion compensation system for tracking and compensating for patient motion during a medical imaging scan comprises an optical marker comprising an optically visible pattern and a mounting portion; a first optical detector positioned to digitally image the optically visible pattern along a first line of sight; a second optical detector positioned to digitally image the optically visible pattern along a second line of sight; a tracking engine configured to determine a pose of the object in six degrees of freedom by analyzing images from the first and second optical detectors; and a controller interface configured to generate tracking information based on the pose and to electronically transmit the tracking information to a scanner controller to enable compensation within a medical imaging scanner for object motion. | 03-17-2016 |
Patent application number | Description | Published |
20100123215 | Capacitor Die Design for Small Form Factors - A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies. | 05-20-2010 |
20100327433 | High Density MIM Capacitor Embedded in a Substrate - An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor. | 12-30-2010 |
20110050334 | Integrated Voltage Regulator with Embedded Passive Device(s) - A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate. | 03-03-2011 |
20110215863 | Integrated Voltage Regulator with Embedded Passive Device(s) - A method of supplying voltage to a die mounted on a packaging substrate includes mounting an active portion of a voltage regulator on the packaging substrate. The method also includes coupling the active portion of the voltage regulator to at least one passive component at least partially embedded in the packaging substrate and coupling the die to the at least one passive component. Mounting the active portion of the voltage regulator includes mounting the die on the packaging substrate where the die includes the active portion of the voltage regulator. | 09-08-2011 |
20110317387 | Integrated Voltage Regulator with Embedded Passive Device(s) for a Stacked IC - A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on. | 12-29-2011 |
20120293972 | Integrated Voltage Regulator Method with Embedded Passive Device(s) - A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias. | 11-22-2012 |
20130285696 | ON-CHIP SENSOR FOR MEASURING DYNAMIC POWER SUPPLY NOISE OF THE SEMICONDUCTOR CHIP - An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured. | 10-31-2013 |