Patent application number | Description | Published |
20130135741 | OPTICAL COATING METHOD, APPARATUS AND PRODUCT - This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.” | 05-30-2013 |
20130263784 | OPTICAL COATING METHOD, APPARATUS AND PRODUCT - This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.” | 10-10-2013 |
20130334031 | PROCESS FOR MAKING OF GLASS ARTICLES WITH OPTICAL AND EASY-TO-CLEAN COATINGS - A process in which both an optical coating, for example, an AR coating, and an ETC coating are deposited on a glass substrate article, in sequential steps, with the optical coating being deposited first and the ETC coating being deposited second, using the same apparatus and without exposing the article to the atmosphere at any time during the application of the optical coating and ETC coating. | 12-19-2013 |
20140016201 | OPTICAL COATING METHOD, APPARATUS AND PRODUCT - This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.” | 01-16-2014 |
20140113083 | PROCESS FOR MAKING OF GLASS ARTICLES WITH OPTICAL AND EASY-TO-CLEAN COATINGS - A process in which both an optical coating, for example, an AR coating, and an ETC coating are deposited on a glass substrate article, in sequential steps, with the optical coating being deposited first and the ETC coating being deposited second, using the same apparatus and without exposing the article to the atmosphere at any time during the application of the optical coating and ETC coating. | 04-24-2014 |
20150015959 | Optical Coating Method, Apparatus and Product - This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.” | 01-15-2015 |
Patent application number | Description | Published |
20080206951 | HIGH PERFORMANCE FIELD EFFECT TRANSISTORS ON SOI SUBSTRATE WITH STRESS-INDUCING MATERIAL AS BURIED INSULATOR AND METHODS - The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer. | 08-28-2008 |
20080217691 | HIGHER PERFORMANCE CMOS ON (110) WAFERS - A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures. | 09-11-2008 |
20080251817 | STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE - A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. | 10-16-2008 |
20080303090 | SUPER HYBRID SOI CMOS DEVICES - The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region. | 12-11-2008 |
20090081836 | METHOD OF FORMING CMOS WITH SI:C SOURCE/DRAIN BY LASER MELTING AND RECRYSTALLIZATION - A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved. | 03-26-2009 |
20090212329 | SUPER HYBRID SOI CMOS DEVICES - The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region. | 08-27-2009 |
20110108943 | HYBRID DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH ENHANCED MOBILITY CHANNELS - A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation. | 05-12-2011 |
20110115004 | EMBEDDED PHOTODETECTOR APPARATUS IN A 3D CMOS CHIP STACK - An embedded photodetector apparatus for a three-dimensional complementary metal oxide semiconductor (CMOS) stacked chip assembly having a CMOS chip and one or more thinned CMOS layers is provided. At least one of the one or more thinned CMOS layers includes an active photodiode area defined within the one or more thinned CMOS layers, the active photodiode area being receptive of an optical signal incident thereon, and the active photodiode area comprising a bulk substrate portion of the thinned CMOS layer. The bulk substrate portion has a diode photodetector formed therein. | 05-19-2011 |
20120208356 | Device component forming method with a trim step prior to sidewall image transfer (SIT) processing - Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed. | 08-16-2012 |
20140103451 | FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS - A fin field-effect transistor (finFET) assembly includes a first finFET device having fins of a first height and a second finFET device having fins of a second height. Each of the first and second finFET devices includes an epitaxial fill material covering source and drain regions of the first and second finFET devices. The epitaxial fill material of the first finFET device has a same height as the epitaxial fill material of the second finFET device. | 04-17-2014 |
20140361338 | REDUCED RESISTANCE SiGe FinFET DEVICES AND METHOD OF FORMING SAME - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins. | 12-11-2014 |
20140361368 | REDUCED RESISTANCE SiGe FinFET DEVICES AND METHOD OF FORMING SAME - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins. | 12-11-2014 |
20150069527 | FINFET DEVICE HAVING A MERGED SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other. | 03-12-2015 |
20150129982 | FinFET DEVICE INCLUDING FINS HAVING A SMALLER THICKNESS IN A CHANNEL REGION, AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a sacrificial gate stack on portions of the fins, forming source drain junctions using ion implantation, forming a dielectric layer on the substrate, removing the sacrificial gate stack to expose the portions of the fins, thinning the exposed portions of the fins to a second thickness less than the first thickness, and forming a gate stack on the thinned exposed portions of the fins to replace the removed sacrificial gate stack. | 05-14-2015 |
20150179789 | FinFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other. | 06-25-2015 |
20150287810 | SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL - A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer. | 10-08-2015 |
20150303281 | FINFET DEVICE WITH VERTICAL SILICIDE ON RECESSED SOURCE/DRAIN EPITAXY REGIONS - A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed. | 10-22-2015 |
20150318218 | SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE - A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel. | 11-05-2015 |
20150318307 | SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE - A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel. | 11-05-2015 |