Otsuka, US
Jim Tidashi Otsuka, San Jose, CA US
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20130195256 | Automated DSL Performance Adjustment - A method includes identifying one or more second digital subscriber lines from one or more first digital subscriber lines based on historical performance data. The one or more second digital subscriber lines are identified based on degraded performance that is determined using first performance information for the one or more first digital subscriber lines. The method includes applying a line profile to the one or more second digital subscriber lines. The method includes storing second performance information associated with the one or more second digital subscriber lines. The method includes sending information to a remote computing device. | 08-01-2013 |
Keisuke Otsuka US
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20150325636 | SEMICONDUCTOR DEVICE - The present invention is characterized by including a plurality of capacitors provided with: a plurality of lower electrodes which extend in a third direction orthogonal to a semiconductor substrate surface; a support film which is positioned flatly and in a manner so as to connect to the upper ends of the outer peripheral side surfaces of the lower electrodes, and which has openings that contain the plurality of lower electrodes; a capacitance insulating film which covers a surface of the lower electrodes; and an upper electrode which covers a surface of the capacitance insulating film. The present invention is also characterized in that the plurality of capacitors comprise: first capacitors provided with first lower electrodes, some of the upper ends of said lower electrodes being positioned in the openings in a planar view; and second capacitors provided with second lower electrodes, the upper ends of said lower electrodes not being positioned in the openings, and in that the first lower electrodes comprise: a first section not positioned in the opening; and a second section positioned in the opening. The upper ends of the first sections are positioned between the upper surface of the support film and the lower surface of the support film, and the upper ends of the second sections are positioned below the lower surface of the support film. The upper ends of the second lower electrodes are positioned between the upper surface of the support film and the lower surface of the support film. | 11-12-2015 |
Mike Otsuka, Sunnyvale, CA US
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20150059422 | SECURITY APPARATUS INCLUDING A REMOTE ACTUATOR ASSEMBLY - A security apparatus for a portable electronic device includes a cable having a length, a first end, and a second end. The security apparatus also includes a lock head coupled to the first end of the cable. The lock head is configured to selectively engage the portable electronic device and is movable by the cable between a first position, in which the lock head is secured to the portable electronic device, and a second position, in which the lock head is unsecured from the portable electronic device. The security apparatus further includes an actuator assembly coupled to the second end of the cable and spaced a distance from the lock head along the length of the cable. The actuator assembly is operable to actuate the cable to move the lock head between the first position and the second position. | 03-05-2015 |
20150240532 | SECURITY APPARATUS INCLUDING A REMOTE ACTUATOR ASSEMBLY - A security apparatus for a portable electronic device includes a cable having a length, a first end, and a second end. The security apparatus also includes a lock head coupled to the first end of the cable. The lock head is configured to selectively engage the portable electronic device and is movable by the cable between a first position, in which the lock head is secured to the portable electronic device, and a second position, in which the lock head is unsecured from the portable electronic device. The security apparatus further includes an actuator assembly coupled to the second end of the cable and spaced a distance from the lock head along the length of the cable. The actuator assembly is operable to actuate the cable to move the lock head between the first position and the second position. | 08-27-2015 |
Tokio Otsuka, Great Neck, NY US
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20150138233 | DEVICES, SYSTEMS, AND METHODS FOR EXAMINING THE INTERACTIONS OF OBJECTS IN AN ENHANCED SCENE - Systems, devices, and methods obtain a sequence of images of a physical scene that includes a physical representation of a first object; calculate a sequence of first transform values of the physical representation of the first object based on the sequence of images; store the sequence of first transform values; generate an enhanced scene; maintain the first object in the enhanced scene at positions and orientations that are indicated by the sequence of first transform values; receive an indication of selected transform values in the sequence of first transform values; retrieve the selected transform values; and generate a replay image of the enhanced scene, from a second observer viewpoint, that shows the first object at the position and the orientation that are indicated by the selected transform values. | 05-21-2015 |
Wataru Otsuka, Boise, ID US
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20140177316 | NON-VOLATILE MEMORY SYSTEM WITH RESET VERIFICATION MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state. | 06-26-2014 |
20140177317 | NON-VOLATILE MEMORY SYSTEM WITH POWER REDUCTION MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system including: providing a resistive storage element having a transformation layer; activating a write driver, coupled to the resistive storage element, for applying a bias voltage to the transformation layer; monitoring a resistance of the resistive storage element by a sense amplifier; and detecting a conductive thread, formed in the transformation layer, by the sense amplifier for reducing a level of the bias voltage. | 06-26-2014 |
20140268975 | INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY STRESS SUPPRESSION AND METHOD OF MANUFACTURE THEREOF - An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line. | 09-18-2014 |
20140268992 | Memory Cells, Memory Systems, and Memory Programming Methods - Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes. | 09-18-2014 |
20140355329 | METHOD AND APPARATUS FOR COMMON SOURCE LINE CHARGE TRANSFER - A method and apparatus for charge transfer comprising a resistive random access memory (ReRAM) cell, coupled to a common source voltage line (CSL) for controlling state of the ReRAM cell, and a charge transfer circuit, coupled to the memory cell through the CSL and a charge consumption circuit, for transferring charge from the CSL to the charge consumption circuit when the state of the memory cell is modified. | 12-04-2014 |
20140362633 | Memory Devices and Memory Operational Methods - Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state. | 12-11-2014 |
20150234603 | MEMORY DEVICE WITH VARIABLE TRIM PARAMETERS - A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled. | 08-20-2015 |
20150294719 | NON-VOLATILE MEMORY SYSTEM WITH RESET VERIFICATION MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state. | 10-15-2015 |