Ong, Penang
Chong-Tee Ong, Penang MY
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20160005720 | Method for Producing an Optoelectronic Device and Optoelectronic Device - A method for producing an optoelectronic device is specified. A housing base body is formed with a self-healing polymer material. A recess is found in the housing base body. The recess is confined by a bottom surface and at least one side wall which are formed at least in places by the plastic material of the base body. An optoelectronic semiconductor chip has a first main surface, a second main surface facing away from the first main surface and at least one side surface connecting the first main surface and the second main surface with each other. The optoelectronic semiconductor chip is placed in the recess, so that the first main surface is brought in contact with the bottom surface and the at least one side surface is brought in contact with the at least one side wall. | 01-07-2016 |
Eng Chuan Ong, Penang MY
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20120205693 | NARROW VIEWING ANGLE PLASTIC LEADED CHIP CARRIER - A Plastic Leaded Chip Carrier (PLCC) package is disclosed. The PLCC package enables a narrow viewing angle without requiring a second lens. In particular, the PLCC package is provided with a reflector cup having multiple stages where the geometry or some other characteristic of one stage is different from the geometry or some other characteristic of another stage. | 08-16-2012 |
20120235188 | Method and Apparatus for a Flat Top Light Source - A light-emitting device and method for manufacturing the device are disclosed. In one embodiment, the light-emitting device comprises a flat substrate and an encapsulation layer formed above the flat substrate. The top portion of the encapsulation layer is flat and the encapsulation layer is divided into a high density layer and a low density layer. The high density layer is formed from a wavelength-converting material precipitated on one side of the encapsulation layer. In the low density layer, the wavelength-converting material exists in particle form suspended within the encapsulation layer. | 09-20-2012 |
20120236529 | Method And Apparatus For A Light Source - A light-emitting device and method for manufacturing the device are disclosed. In one embodiment, an optical coupling layer can formed on a substrate encapsulating a light source die. An encapsulation layer can be formed on the optical coupling layer. A top portion of the encapsulation layer can be flat and the encapsulation can comprise a high density layer and a low density layer. The high density layer can comprise wavelength-converting material precipitated on one side of the encapsulation layer. The low density layer can comprise the wavelength-converting material in particle form suspended within the encapsulation layer. In another embodiment, the method for making the light-emitting device is disclosed. | 09-20-2012 |
20130050982 | Method And Apparatus For A Light Source - A light-emitting device having a light source die mounted within an aperture is disclosed. The aperture is covered by a die attach pad on one side. The light source die is mounted on a die attach pad within the aperture. In one embodiment, an optical coupling layer can be formed within an aperture encapsulating a light source die. A wavelength converting layer can be formed on the substrate above the optical coupling layer. The wavelength converting layer can comprise a high density layer and a low density layer. The high density layer can comprise wavelength-converting material precipitated on one side of the wavelength converting layer. The low density layer can comprise the wavelength-converting material in particle form suspended within the wavelength converting layer. In one embodiment, the wavelength converting layer may be confined within the aperture of the substrate. | 02-28-2013 |
20140175486 | NARROW VIEWING ANGLE PLASTIC LEADED CHIP CARRIER - The PLCC package enables a narrow viewing angle without requiring a second lens by providing the PLCC package with a reflector cup having multiple stages where the geometry or some other characteristic of one stage is different from the geometry or some other characteristic of another stage. | 06-26-2014 |
20140252399 | ELECTRONIC PACKAGING SUBSTRATE WITH ETCHING INDENTATION AS DIE ATTACHMENT ANCHOR AND METHOD OF MANUFACTURING THE SAME - An electronics package is disclosed. The electronics package is disclosed as including a substrate core, a metal layer established on top of the substrate core, the metal layer being etched so as to include a die attachment anchor and at least one gap that separates a die bonding pad from at least one of a trace and wire bonding pad, for example. The die attachment anchor is established on top of the die bonding pad and has a depth that does not extend all the way through the die bonding pad. | 09-11-2014 |
Hean Kooi Ong, Penang MY
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20110113528 | GLOVE WITH LIQUID STORAGE AND DISPENSATION CAPABILITIES - The present invention is a hand covering such as a glove that is adapted to absorb and store an amount of liquid within an adsorbent layer incorporated into the glove. The liquid can be easily dispensed by certain movements of the hand such as squeezing or grasping. The glove design allows another, external layer purpose-engineered for particular applications to be either permanently or detachably attached on the exterior of the glove. The rubber used is a composite comprising 10-20% nitrile and the remaining 80-90% natural latex. | 05-19-2011 |
Hui-Peng Ong, Penang MY
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20080315906 | FAULTY DANGLING METAL ROUTE DETECTION - A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection. | 12-25-2008 |
20120151430 | STRESS REDUCTION ON VIAS AND YIELD IMPROVEMENT IN LAYOUT DESIGN THROUGH AUTO GENERATION OF VIA FILL - A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout. | 06-14-2012 |
Jin Ngee Ong, Penang MY
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20100142718 | NOISE CANCELLING HEADPHONE - A noise cancelling headphone is described. The noise cancelling headphone utilizes a low power consuming noise cancellation circuit wherein an audio input signal is directly fed into the headphone without the use of an additional headphone amplifier. The noise cancelling circuit uses a microphone to pick up ambient noise and produces a signal which is equal in amplitude but opposite in polarity to the ambient noise signal. The resultant signal is mixed with the audio input signal and fed into the speakers of the headphone. This method is advantageous because it uses fewer components than conventional noise cancellation circuits and it also consumes less power due to the use of fewer components. The distortion of the audio input signal is also reduced since no amplification is performed to the audio input signal onboard the noise cancellation circuit. | 06-10-2010 |
Joon-Heong Ong, Penang MY
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20090206386 | DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES - One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further comprises a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level. Other methods and circuits are also disclosed. | 08-20-2009 |
Kang Eu Ong, Penang MY
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20090321928 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 12-31-2009 |
20150076692 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 03-19-2015 |
Kenryuu Ley Keong Ong, Penang MY
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20120164442 | Flame Retardant Multi-Layer Label - The present invention relates to a multi-layer label, including: a backing film having a first surface and a second surface, and a topcoat layer containing a polymeric matrix and a flame retardant and having a first surface and a second surface, the second surface of the topcoat in intimate contact with the first surface of the backing film, in which the label as a whole is in compliance with UL94 VTM-0 standard and comprises less than 900 ppm of chlorine, less than 900 ppm of bromine, and less than 1500 ppm of chlorine and bromine in combination. The multi-layer label may further include a flame retardant layer containing a binder and a flame retardant, and/or an adhesive layer optionally containing a flame retardant. The multi-layer label is useful in electronic products and mass transportation. | 06-28-2012 |
Kiam Soon Ong, Penang MY
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20090129085 | OPTICAL DEVICE - An exemplary embodiment of an optical device may include a lead frame with a plurality of leads and a reflector housing formed around the lead frame. The reflector housing includes a first end face and a second end face and a peripheral sidewall extending between the first end face and the second end face. The reflector housing includes a first pocket with a pocket opening in the first end face and a second pocket with a pocket opening in the second end face. At least one LED die is mounted in the first pocket of the reflector housing, and a light transmitting encapsulant is disposed in the first pocket and encapsulating the at least one LED die. | 05-21-2009 |
20100320485 | MULTI-CHIP PACKAGED LED LIGHT SOURCE - A light source having a lead frame, a body, and a plurality of dies, each die having an LED thereon is disclosed. The body includes a top surface, a bottom surface and a plurality of side surfaces. The lead frame includes first, second, and third sections, the first section includes a die mounting area having a first protrusion that passes through the body and terminates in a pad on the bottom surface. The second and third sections each include a protrusion that is bent to form first and second leads that run along one of the side surfaces. Each die is bonded to the die mounting area such that a first contact is electrically connected to the die mounting area, and a second contact is connected to one of the second and third sections. The first protrusion of the first section provides improved heat transfer. | 12-23-2010 |
20130307013 | LIGHT EMITTING DEVICE WITH DARK LAYER - A light-emitting device having a plurality of leads, a body, a light source die, a dark layer, and a substantially transparent encapsulant is disclosed. The dark layer absorbs a substantial portion of ambient light. The light source die may be a top emitting die. The light-emitting devices may be suitable for applications such as a large scale electronic display where each pixel is represented by each light-emitting device. The dark layer may contribute towards high contrast ratio by absorbing substantial amount of ambient light falling thereon. | 11-21-2013 |
20140312371 | HYBRID REFLECTOR CUP - A package for a light source and methods of manufacturing the same are disclosed. In particular, a light source package is disclosed with an outer component and an interchangeable inner component. The inner component can be modular and replaceable with other inner components having different properties, thereby enabling a flexible design of a light source package to accommodate different lighting conditions and desired lighting effects. | 10-23-2014 |
20150228608 | Semiconductor Device With An Interlocking Wire Bond - In one embodiment, a semiconductor device having a die attach pad, an interlocking wire bond, a semiconductor die and an adhesive material is disclosed. The adhesive material may be configured to adjoin the semiconductor die and the die attach pad. A portion of the interlocking wire bond may be submerged within the adhesive material. In another embodiment, a device having a semiconductor die, a die attach glue and a die attach pad is disclosed. The device may comprise an interlock bonding structure submerged within the adhesive material. In yet another embodiment, a light-emitting device comprising an interlock structure is disclosed. | 08-13-2015 |
20150228611 | SEMICONDUCTOR DEVICE WITH AN INTERLOCKING STRUCTURE - In one embodiment, a semiconductor device having a die attach pad, a semiconductor die and an adhesive material is disclosed. The adhesive material may be configured to adjoin the semiconductor die and the die attach pad. The die attach pad may be sandwiched between the semiconductor die and the die attach pad. In another embodiment, a device having a semiconductor die, a die attach glue and a die attach pad is disclosed. The device may comprise an interlock structure formed integrally with the die attach pad. In yet another embodiment, a light-emitting device comprising an interlock structure is disclosed. | 08-13-2015 |
Lay Koon Ong, Penang MY
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20110122630 | Solid State Lamp Having Vapor Chamber - A solid state lamp has a form that replaces a standard screw-in or plug-in type light bulb. One or more LEDs are mounted on a thermally conductive submount, which is mounted on the top surface of a substantially round and flat vapor chamber. The vapor chamber efficiently spreads the heat and also conducts heat vertically. The vapor chamber is affixed to a substantially round mounting base of a metal housing. In this way, the very small LED dies appear to the mounting base as much larger heat sources producing less heat per unit area, and the thermal resistance of the heat path is greatly reduced. The housing has ventilation openings for cooling a bottom surface of the mounting base. The top of the vapor chamber is highly reflective, and the housing has a high emissivity coating. A standard base is attached to the housing for connection to an AC mains voltage. | 05-26-2011 |
Mee-Choo Ong, Penang MY
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20100302846 | CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY - A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then be programmed. This will change the defective un-programmed cell to a new programmed value. To account for the location of the failing memory cell, address syndrome bits are used to identify the location of the defective memory cell. | 12-02-2010 |
20150149696 | Auto Resume of Irregular Erase Stoppage of a Memory Sector - Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed. | 05-28-2015 |
20150253988 | Memory Access Bases on Erase Cycle Time - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality Of indicators for the memory block. The indicator is saved and later retrieved during a read operation. | 09-10-2015 |
Tean Wee Ong, Penang MY
Patent application number | Description | Published |
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20090321928 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 12-31-2009 |
20150076692 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 03-19-2015 |
Tze Mei Ong, Penang MY
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20150186311 | SMART DIRECT MEMORY ACCESS - Disclosed herein is a memory access controller. The memory access controller includes an event detection unit (EDU) to receive an indication that a trigger event has been detected in an electronic component, wherein the EDU is to select a memory access context based on the trigger event. The memory access controller includes an event selector to start a DMA operation based on the memory context. | 07-02-2015 |
Wei-Kent Ong, Penang MY
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20130219137 | REDUNDANCY LOADING EFFICIENCY - A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors. | 08-22-2013 |
20150149696 | Auto Resume of Irregular Erase Stoppage of a Memory Sector - Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed. | 05-28-2015 |
20150253988 | Memory Access Bases on Erase Cycle Time - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality Of indicators for the memory block. The indicator is saved and later retrieved during a read operation. | 09-10-2015 |