| Patent application number | Description | Published |
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| 20080268621 | METHOD FOR MANUFACTURING COMPOUND MATERIAL WAFER AND CORRESPONDING COMPOUND MATERIAL WAFER - The invention relates to methods for manufacturing compound material wafers, in particular silicon on insulator wafers, by the steps of providing a donor substrate, forming an insulating layer, providing a handle substrate, creating a predetermined splitting area in the donor substrate, attaching the donor substrate to the handle substrate and detaching at the predetermined splitting area to achieve the compound material wafer. In order to be able to more often reuse the remainder of the donor substrate in subsequent manufacturing runs, various embodiments are disclosed, such as the insulating layer can be provided on the donor substrate at a maximum thickness of 500 A, or that the insulating layer can be provided by deposition or only upon the handle substrate. Alternatively, no insulating layer is provided so that the donor and handle substrates can have different crystal orientations. | 10-30-2008 |
| 20090032911 | PATTERNED THIN SOI - A process for treating a structure to prepare it for electronics or optoelectronics applications. The structure includes a bulk substrate, an oxide layer, and a semiconductor layer, and the process includes providing a masking to define on the semiconductor layer a desired pattern, and applying a thermal treatment for removing a controlled thickness of oxide in the regions of the oxide layer corresponding to the desired pattern to assist in preparing the structure. | 02-05-2009 |
| 20100038756 | (110) ORIENTED SILICON SUBSTRATE AND A BONDED PAIR OF SUBSTRATES COMPRISING SAID (110) ORIENTED SILICON SUBSTRATE - The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates comprising a first silicon substrate with (100) orientation and a second silicon substrate with (110) orientation. It is the object of the present invention to provide methods and substrates of the above mentioned type with a high efficiency wherein the formed (110) substrate has at least near and at its surface virtually no defects. The object is solved by a method of fabricating a silicon substrate with (110) orientation and by a method of fabricating a bonded pair of silicon substrates, comprising the steps of providing a basic silicon substrate with (110) orientation, said basic silicon substrate having a roughness being equal or less than 0.15 nm RMS in a 2×2 μm | 02-18-2010 |
| 20100188094 | METHOD AND APPARATUS FOR MEASURING A LIFETIME OF CHARGE CARRIERS - An apparatus for measuring a lifetime of charge carriers that has a measuring probe and a component for directing ultraviolet radiation to a measuring position. The measuring probe also includes at least one electrode provided at a predetermined spatial relationship to the measuring position. A microwave source is adapted to direct microwave radiation to the measuring position, a microwave detector is adapted to measure an alteration of an intensity of microwave radiation reflected at the measuring position in response to the ultraviolet radiation and a semiconductor structure holder is adapted to receive a semiconductor structure and to provide an electric contact to a portion of the semiconductor structure. Additionally, a device for moving the substrate holder relative to the measuring probe is provided for positioning at least one portion of the semiconductor structure at the measuring position. The apparatus includes a power source adapted to apply a bias voltage between the semiconductor structure holder and the electrode. | 07-29-2010 |
| 20110097871 | Process for the transfer of a thin layer formed in a substrate with vacancy clusters - Methods for forming semiconductor structures comprising a layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect of defects, and resulting structures therefrom. For example, a semiconductor on insulator (SeOI) structure can be formed by a method comprising: —providing a donor substrate ( | 04-28-2011 |
| 20110180912 | PATTERNED THIN SOI - A semiconductor structure for electronics or optoelectronics that includes successively a bulk substrate, an oxide layer and a semiconductor layer, wherein the oxide layer comprises regions of different thicknesses which are selectively controlled. | 07-28-2011 |
| 20110183493 | PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE - The present invention relates to a process for manufacturing a structure comprising a germanium layer ( | 07-28-2011 |
| 20110193201 | METHOD TO FABRICATE AND TREAT A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE, ENABLING DISPLACEMENT OF DISLOCATIONS, AND CORRESPONDING STRUCTURE - The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate ( | 08-11-2011 |
| 20110275226 | PROCESS TO DISSOLVE THE OXIDE LAYER IN THE PERIPHERAL RING OF A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE - The invention concerns a process to treat a structure of semiconductor-on-insulator type structure of a carrier substrate, an oxide layer and a thin layer of a semiconductor material, wherein the structure having a peripheral ring in which the oxide layer is exposed, and the process includes the application of a main thermal treatment in a neutral or controlled reducing atmosphere. The method includes a step to cover at least an exposed peripheral part of the oxide layer, prior to the main thermal treatment, this latter treatment being conducted under controlled time and temperature conditions so as to urge at least part of the oxygen in the oxide layer to diffuse through the thin semiconductor layer, leading to controlled reduction of the thickness of the oxide layer. | 11-10-2011 |
| 20120094496 | Process For Locally Dissolving The Oxide Layer In A Semiconductor-On-Insulator Type Structure - A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer. | 04-19-2012 |
| 20130294038 | ELECTRONIC DEVICE FOR RADIOFREQUENCY OR POWER APPLICATIONS AND PROCESS FOR MANUFACTURING SUCH A DEVICE - The invention relates to an electronic device for radio frequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/m K and a superficial layer having a thickness of at least 5 μm, the superficial layer having an electrical resistivity of at least 3000 Ohm·cm and a thermal conductivity of at least 30 W/m K. The invention also relates to two processes for manufacturing such a device. | 11-07-2013 |
| 20140027714 | QUANTUM WELL THERMOELECTRIC COMPONENT FOR USE IN A THERMOELECTRIC DEVICE - A quantum well thermoelectric component for use in a thermoelectric device based on the thermoelectric effect,
| 01-30-2014 |
| 20140030877 | PROCESS TO DISSOLVE THE OXIDE LAYER IN THE PERIPHERAL RING OF A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE - A process for avoiding formation of a Si—SiO | 01-30-2014 |
| 20140370695 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The present invention relates to a method for fabricating a semiconductor structure comprising a semiconductor layer and a metallic layer, to improve the breakdown voltage properties of the device and reduce leakage currents, the method comprises the steps of a) providing a semiconductor layer comprising defects and/or dislocations; b) removing material at one or more locations of the defects and/or dislocations thereby forming pits in the semiconductor layer, c) passivating the pits, and c) providing the metallic layer over the semiconductor layer. The invention also relates to a corresponding semiconductor structure. | 12-18-2014 |
| 20140374886 | METHOD FOR FABRICATING A SUBSTRATE AND SEMICONDUCTOR STRUCTURE - The invention relates to a method for fabricating a substrate, comprising the steps of providing a donor substrate with at least one free surface, performing an ion implantation at a predetermined depth of the donor substrate to form an in-depth predetermined splitting area inside the donor substrate, and is characterized in providing a layer of an adhesive, in particular an adhesive paste, over the at least one free surface of the donor substrate. The invention further relates to a semiconductor structure comprising a semiconductor layer, and a layer of a ceramic-based and/or a graphite-based and/or a metal-based adhesive provided on one main side of the semiconductor layer. | 12-25-2014 |
| 20150014824 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The present invention relates to a method for fabricating a substrate for a semiconductor device comprising an interface region between a first layer and a second layer having different electrical properties and an exposed surface, wherein at least the second layer includes defects and/or dislocations, the method comprising the steps of: a) removing material at one or more locations of the defects and/or dislocations, thereby forming pits, wherein the pits intersect the interface region, and b) passivating the pits. The invention also relates to a corresponding semiconductor device structure. | 01-15-2015 |
| Patent application number | Description | Published |
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| 20100052092 | METHOD FOR FABRICATING A SEMICONDUCTOR ON INSULATOR SUBSTRATE WITH REDUCED SECCO DEFECT DENSITY - The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm | 03-04-2010 |
| 20100087049 | RELAXATION OF A STRAINED MATERIAL LAYER WITH APPLICATION OF A STIFFENER - The invention relates to methods of fabricating a layer of at least partially relaxed material, such as for electronics, optoelectronics or photovoltaics. An exemplary method includes supplying a structure that includes a layer of strained material situated between a reflow layer and a stiffener layer. The method further includes applying a heat treatment that brings the reflow layer to a temperature equal to or greater than the glass transition temperature of the reflow layer, and the thickness of the stiffener layer is progressively reduced during heat treatment. The invention also relates to an exemplary method of fabricating semiconductor devices on a layer of at least partially relaxed material. Specifically, at least one active layer may be formed on the at least partially relaxed material layer. The active layer may include laser components, photovoltaic components and/or electroluminescent diodes. | 04-08-2010 |
| 20100193899 | PRECISE OXIDE DISSOLUTION - In a Semiconductor-on-Insulator (SeOI) wafer that includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer, a method of decreasing the thickness of the BOX layer by dissolving it at a dissolution rate that is controlled and set to be below 0.06 Å/sec in order to avoid increasing Dit. The Dit after dissolution of the BOX layer is typically below 1E12 cm-2 eV-1. | 08-05-2010 |
| 20100264458 | METHOD FOR MANUFACTURING HETEROSTRUCTURES - A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure. | 10-21-2010 |
| 20100283118 | OXIDATION AFTER OXIDE DISSOLUTION - A method for manufacturing a SeOI substrate that includes a thin working layer made from one or more semiconductor material(s); a support layer; and a thin buried oxide layer between the working layer and the support layer. The method includes a manufacturing step of an intermediate SeOI substrate having a buried oxide layer with a thickness greater than a thickness desired for the thin buried oxide layer; and a dissolution step of the buried oxide layer in order to form therewith the thin buried oxide layer. After the dissolution step, an oxidation step of the substrate is conducted for creating an oxidized layer on the substrate, and an oxide migration step for diffusing at least a part of the oxide layer through the working layer in order to increase the electrical interface quality of the substrate and decrease its Dit value. | 11-11-2010 |
| 20110127581 | HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR PHOTOVOLTAIC COMPONENTS - The present invention relates to a support for the epitaxy of a layer of a material of composition Al | 06-02-2011 |
| 20120190170 | PRECISE OXIDE DISSOLUTION - A method for dissolving the buried oxide layer of a SeOI wafer in order to decrease its thickness. The SeOI wafer includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer. The dissolution rate of the buried oxide layer is controlled and set to be below 0.06 Å/sec. | 07-26-2012 |
| 20120244687 | METHOD OF MANUFACTURING A BASE SUBSTRATE FOR A SEMI-CONDUCTOR ON INSULATOR TYPE SUBSTRATE - A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure. | 09-27-2012 |
