Patent application number | Description | Published |
20080206965 | STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY - Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices. | 08-28-2008 |
20080242069 | HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS - Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects. | 10-02-2008 |
20080265282 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 10-30-2008 |
20080265931 | On-chip electromigration monitoring - A method is provided for monitoring interconnect resistance within a semiconductor chip assembly. A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition. | 10-30-2008 |
20080299732 | METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS - A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor. | 12-04-2008 |
20090032840 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in source and drain regions of an NFET device and an embedded SiGe layer in source and drain regions of a PFET device. The PFET device is subject to compressive strain. The method includes embedding SiGe in source and drain regions of an NFET device and implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device. The SiGeC is melt laser annealed to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe. | 02-05-2009 |
20090108300 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 04-30-2009 |
20090132985 | Design structure for on-chip electromigration monitoring system - A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined. | 05-21-2009 |
20090142894 | METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region. | 06-04-2009 |
20090146181 | INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS - An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer. | 06-11-2009 |
20090155487 | ULTRAVIOLET UV PHOTO PROCESSING OR CURING OF THIN FILMS WITH SURFACE TREATMENT - A method provides an etching ambient environment within an ultraviolet curing chamber and can optionally also generate an electrical discharge in the chamber. The method also irradiates the substrate with ultraviolet radiation. The providing of the etching ambient environment, the generating of the electrical discharge, and the irradiating can be performed simultaneously. Alternatively, the providing of the etching ambient environment and the generating of the electrical discharge can be used as a pre-treatment and performed before the irradiating. The etching ambient environment and the generating of the electrical discharge can be provided in such concentrations that the etching ambient environment removes hydrogen and/or oxygen from the deposited thin film. | 06-18-2009 |
20090166770 | METHOD OF FABRICATING GATE ELECTRODE FOR GATE OF MOSFET AND STRUCTURE THEREOF - A method of fabricating a gate electrode for a gate of a metal oxide semiconductor field effect transistor (MOSFET), where the transistor has a structure incorporating a gate disposed on a substrate. The substrate comprises a source-drain region. The gate includes a gate electrode disposed on a gate dielectric and surrounded by a spacer. The gate electrode includes a capping layer of polysilicon (poly-Si) and a thin polycrystalline intermixed silicon-germanium (SiGe) layer superposed on the gate dielectric. The thin polycrystalline intermixed silicon-germanium (SiGe) layer may be formed by a high-temperature ultrafast melt-crystalization annealing process. The melt-crystallization process of the intermixed silicon-germanium provides an active dopant concentration that reduces the width of a depletion region formed at an interface of the polycrystalline intermixed silicon-germanium (SiGe) layer and the gate dielectric. | 07-02-2009 |
20090267149 | SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS - In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC. | 10-29-2009 |
20090302387 | INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF - An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions. | 12-10-2009 |
20090317924 | METHOD FOR OPTIMIZING THE ROUTING OF WAFERS/LOTS BASED ON YIELD - A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for increasing overall yield in semiconductor manufacturing includes a module for routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from the tools processing the wafers or wafer lots. | 12-24-2009 |
20100080446 | INLINE LOW-DAMAGE AUTOMATED FAILURE ANALYSIS - A system and method for failure analysis of devices on a semiconductor wafer is disclosed. The present invention comprises the use of an inline focused ion beam milling tool to perform milling and image capturing of cross sections of a desired inspection point. The inspection points are located by identifying at least one fiducial that corresponds to an X-Y offset from the desired inspection point. The fiducials are recognized by a computer vision system. By automating the inspection process, the time required to perform the inspections is greatly reduced. | 04-01-2010 |
20100159664 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 06-24-2010 |
20120146092 | STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE - While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices. | 06-14-2012 |
20120149159 | STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE - While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices. | 06-14-2012 |
20130210210 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 08-15-2013 |
20140103366 | SILICON DEVICE ON SI:C-OI AND SGOI AND METHOD OF MANUFACTURE - A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island. | 04-17-2014 |