Patent application number | Description | Published |
20100312988 | Data processing apparatus and method for handling vector instructions - A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes. The vector processing unit is responsive to a vector operation instruction to perform an operation in parallel on data elements input to the plurality of lanes of parallel processing, but to exclude from the performance of the operation any lane whose associated skip indicator is set. This allows the operation specified by vector instructions to be performed conditionally within each of the lanes of parallel processing without any modification to the vector instructions that are specifying those operations. | 12-09-2010 |
20110087858 | Memory management unit - A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided. | 04-14-2011 |
20110150090 | Video encoder - A video encoding apparatus for encoding a video stream comprising: a reference frame cache configured to cache reference frame video data retrieved from a reference frame storage unit in external memory, the reference frame video data cached in the reference frame cache being derived from an individual frame of the video stream; a first source frame storage unit configured to store a first block of unencoded video data taken from a first source frame of the video stream; a second source frame storage unit configured to store a second block of unencoded video data taken from a second source frame of the video stream; a first video encoder configured to perform a first encoding operation to encode the first block of unencoded video data with reference to the reference frame video data cached in the reference frame cache; and a second video encoder configured to perform a second encoding operation to encode said second block of unencoded video data with reference to the reference frame video data cached in the reference frame cache, wherein the first video encoder and the second video encoder are configured to perform the first encoding operation and the second encoding operation in parallel with one another. | 06-23-2011 |
20110191539 | Coprocessor session switching - A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data. | 08-04-2011 |
20110206133 | Parallel parsing in a video decoder - A video decoder configured to decode an encoded video bitstream comprises a first parsing unit and a second parsing unit, each configured to independently parse the encoded video bitstream to derive parsing state information therefrom on which subsequent parsing of the encoded video bitstream at least partially depends and to identify macroblock information for decoding. The encoded video bitstream comprises frame header information defining a sequence of frames and each frame is composed of macroblocks represented by macroblock information. A control unit of the video encoder allocates each frame of macroblock information to one of the two parsing units to parse. The two parsing units are both configured to parse frame header information to thereby each derive parsing state information for the encoded video bitstream, and the two parsing unit are each configured to parse macroblock information allocated to them, skipping macroblock information allocated to the other parsing unit. | 08-25-2011 |
20120213290 | Parallel video decoding - A video decoding apparatus and method are disclosed. The video decoding apparatus comprises at least one parsing unit configured to receive input video data as an encoded video bitstream which contains sequential internal dependencies. The at least one parsing unit is configured to perform a parsing operation on the encoded video bitstream to generate an intermediate representation of the input video data in which at least a subset of the sequential internal dependencies are resolved. The intermediate representation of the input video data can be stored in a buffer. The video decoding apparatus further comprises a reconstruction unit configured to retrieve in parallel a plurality of input streams of the intermediate representation and to perform a decoding operation on the plurality of input streams in parallel to generate decoded output video data. | 08-23-2012 |
20130036290 | METHODS OF AND APPARATUS FOR STORING DATA IN MEMORY IN DATA PROCESSING SYSTEMS - A data array | 02-07-2013 |
20130195352 | METHODS OF AND APPARATUS FOR ENCODING AND DECODING DATA IN DATA PROCESSING SYSTEMS - To encode and compress a data array | 08-01-2013 |
20130198485 | METHODS OF AND APPARATUS FOR STORING DATA IN MEMORY IN DATA PROCESSING SYSTEMS - A data array | 08-01-2013 |
20130275701 | MANAGEMENT OF DATA PROCESSING SECURITY IN A SECONDARY PROCESSOR - A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of descriptors defining the translations, wherein the page table base address is defined by the primary processor and cannot be amended by the secondary processor. | 10-17-2013 |
20130276096 | MANAGEMENT OF DATA PROCESSING SECURITY IN A SECONDARY PROCESSOR - A data processing apparatus is configured to perform secure data processing operations and non-secure data processing operations, wherein the apparatus includes a master device with a secure domain and a non-secure domain. Components of the master device operate in the secure domain when performing secure data processing operations and operate in the non-secure domain when performing the non-secure data processing operations. A slave device is configured to perform a delegated data processing operation specified by the master device and a communication bus connecting the master device to the slave device. The delegated operation is initiated by an issuing component in the master device, wherein the slave device includes a security inheritance mechanism configured to cause the delegated operation to inherit a non-secure security status or a secure status depending upon whether the issuing component in the master device is operating in the non-secure domain or the secure domain. | 10-17-2013 |
20140283117 | PROTECTION UNIT AND METHOD FOR CONTROLLING ACCESS BY PLURAL PROCESSES TO A STORAGE UNIT - A data processing apparatus is provided, comprising plural processing units configured to execute plural processes, a storage unit configured to store data required for the plural processes; and a protection unit configured to control access by the plural processes to the storage unit. The protection unit is configured to define an allocated access region of the storage unit for each process of the plural processes, wherein the protection unit is configured to deny access for each the process outside the allocated access region and wherein allocated access regions are defined to be non-overlapping. The protection unit is configured to define each allocated access region as a contiguous portion of the storage unit between a lower region limit and an upper region limit, and the protection unit is configured such that when the lower region limit is modified the lower region limit cannot be decreased and such that when the upper region limit is modified the upper region limit cannot be decreased. | 09-18-2014 |
20150089148 | MEMORY MANAGEMENT UNIT - A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided. | 03-26-2015 |