Ohuchi
Atsushi Ohuchi US
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20110151036 | AROMATASE ACTIVATOR - A method of increasing expression of the aromatase gene by treating a cell population with an effective amount of an aromatase activator containing an extract of | 06-23-2011 |
Kazuya Ohuchi, Somers, NY US
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20120242356 | SPECIFIC CONTACT RESISTIVITY MEASUREMENT METHOD, SEMICONDUCTOR DEVICE FOR SPECIFIC CONTACT RESISTIVITY MEASUREMENT, AND METHOD FOR MANUFACTURING THE SAME - A test structure, a method of employing the test structure, and a method of manufacturing the test structure are provided for measuring a contact resistance between a silicide and a semiconductor. The test structure includes a set of silicide layers separated from one another and upon which electrodes from a set of electrodes are placed. One pair of electrodes is employed to force a constant current through the silicide layers and a diffusion layer of a semiconductor substrate of the test structure. Another pair of electrodes determines a potential drop between the silicide layers and the diffusion layer. Based upon the constant current and the potential drop determined, a contact resistance is extracted. | 09-27-2012 |
Masahiko Ohuchi, Taichung City TW
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20130130463 | MANUFACTURING METHOD OF CHARGING CAPACITY STRUCTURE - A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes. | 05-23-2013 |
20130146561 | METHOD OF MANUFACTURING VERTICAL TRANSISTORS - A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted. | 06-13-2013 |