Patent application number | Description | Published |
20100196592 | METHODS OF FABRICATING CAPACITORS INCLUDING LOW-TEMPERATURE CAPPING LAYERS - In a method of fabricating a capacitor, a lower electrode is formed, and a dielectric layer is formed on the lower electrode. An upper electrode is foamed on the dielectric layer opposite the lower electrode. A low-temperature capping layer is formed on the upper electrode at a temperature of less than about 300° C. Related devices and fabrication methods are also discussed. | 08-05-2010 |
20100209595 | Methods of Forming Strontium Ruthenate Thin Films and Methods of Manufacturing Capacitors Including the Same - In a method of forming a strontium ruthenate thin film using water vapor as an oxidizing agent, a strontium source and a ruthenium source are used. The strontium source includes a cyclopentadienyl (Cp) ligand, an alkoxide ligand, an alkyl ligand, an amide ligand or a halide ligand, and the ruthenium source includes a beta diketonate ligand. | 08-19-2010 |
20110242727 | CAPACITOR - A capacitor may include a lower electrode structure, a dielectric layer and an upper electrode structure. The lower electrode structure may include a first lower pattern, a first deformation-preventing layer pattern and a second lower pattern. The first lower pattern may have a cylindrical shape. The first deformation-preventing layer pattern may be formed on an inner surface of the first lower pattern. The second lower pattern may be formed on the first deformation-preventing layer pattern. The dielectric layer may be formed on the lower electrode structure. The upper electrode structure may be formed on the dielectric layer. Thus, the capacitor may have a high capacitance and improved electrical characteristics. | 10-06-2011 |
20120086014 | Semiconductor Device Having Glue Layer And Supporter - A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials. | 04-12-2012 |
20120119327 | CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR - A capacitor in a semiconductor memory device comprises a lower electrode on a substrate that is formed of a conductive metal oxide having a rutile crystalline structure, a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and includes impurities for reducing a leakage current, and an upper electrode on the titanium oxide dielectric layer. A method of forming a capacitor in a semiconductor device comprise steps of forming a lower electrode on a substrate that includes a conductive metal oxide having a rutile crystalline structure, forming a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and impurities for reducing a leakage current, and forming an upper electrode on the titanium oxide dielectric layer. | 05-17-2012 |
20120299072 | SEMICONDUCTOR DEVICE HAVING METAL PLUG AND METHOD OF FORMING THE SAME - Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide. | 11-29-2012 |
20130208535 | RESISTIVE MEMORY DEVICE AND METHOD OF WRITING DATA USING MULTI-MODE SWITCHING CURRENT - A method of writing data in a resistive memory device includes performing a test operation to distinguish normal memory cells from weak memory cells, during a write operation directed to normal memory cells using a write current and during a weak write operation directed to weak memory cells using a higher write current. | 08-15-2013 |
20130217203 | CAPACITOR, METHOD OF FORMING A CAPACITOR, SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A capacitor in a semiconductor memory device comprises a lower electrode on a substrate that is formed of a conductive metal oxide having a rutile crystalline structure, a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and includes impurities for reducing a leakage current, and an upper electrode on the titanium oxide dielectric layer. A method of forming a capacitor in a semiconductor device comprise steps of forming a lower electrode on a substrate that includes a conductive metal oxide having a rutile crystalline structure, forming a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and impurities for reducing a leakage current, and forming an upper electrode on the titanium oxide dielectric layer. | 08-22-2013 |
20140013034 | NONVOLATILE RANDOM ACCESS MEMORY AND DATA MANAGEMENT METHOD - A data management method for a main memory including a memory controller and a nonvolatile RAM includes; designating code page data temporarily stored in a standby area of the nonvolatile RAM as set, copying the code page data from the standby area to an in-use area of the nonvolatile RAM, designating the code page data stored in the in-use area as reset, and thereafter, during rebooting of a user device incorporating the main memory, invalidating the reset code page data while retaining the set code page data in the nonvolatile RAM. | 01-09-2014 |
20140013036 | USER DEVICE HAVING NONVOLATILE RANDOM ACCESS MEMORY AND METHOD OF BOOTING THE SAME - Disclosed is a method of booting a user device including a nonvolatile random access memory (RAM) and a mode register. The method includes reading a Basic Input/Output System (BIOS) refresh setting during a booting operation, and setting the mode register to a refresh timing mode of the nonvolatile RAM according to the BIOS refresh setting. The refresh timing mode selectively includes a refresh inactivation mode for inactivating a refresh operation of the nonvolatile RAM or a refresh execution mode of multiple refresh execution modes having corresponding different refresh periods for activating the refresh operation of the nonvolatile RAM. | 01-09-2014 |
20140145306 | SEMICONDUCTOR DEVICE HAVING GLUE LAYER AND SUPPORTER - A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5 eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials. | 05-29-2014 |
20140146603 | NONVOLATILE MEMORY DEVICE INCLUDING SUDDEN POWER OFF DETECTION CIRCUIT AND SUDDEN POWER OFF DETECTION METHOD THEREOF - A nonvolatile memory device includes a memory cell array comprising memory cells connected to bit lines and word lines; a word line decoder configured to apply word line voltages to the word lines; a bit line selector configured to select at least one bit line of the bit lines; a control logic configured to control the word line decoder and the bit line selector so that write data is programmed in the memory cell array; and a sudden power off (SPO) detection circuit, wherein the SPO detection circuit comprises: a sensing cell; a first driver configured to provide a first voltage to the sensing cell; and a second driver configured to provide a second voltage to the sensing cell, wherein a program state of the sensing cell becomes different depending on an order or a time difference between the first driver and the second driver being powered off. | 05-29-2014 |