| Patent application number | Description | Published |
|---|
| 20120257455 | NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING NONVOLATILE MEMORY DEVICES - Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to the input command and address, and applying a specific voltage to memory cells of cell strings corresponding to the input address during the determined voltage applying time. | 10-11-2012 |
| 20130031443 | METHOD OF OPERATING MEMORY CONTROLLER, AND MEMORY SYSTEM, MEMORY CARD AND PORTABLE ELECTRONIC DEVICE INCLUDING THE MEMORY CONTROLLER - A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages. | 01-31-2013 |
| 20130198440 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND BLOCK MANAGING METHOD, AND PROGRAM AND ERASE METHODS THEREOF - In one embodiment, the method includes overwriting a memory cell storing m-bit data to store n-bit data, where n is less than or equal to m. The memory cell has one of a first plurality of program states when storing the m-bit data, and the memory cell has one of a second plurality of program states when storing the n-bit data. The second plurality of program states include at least one program state not in the first plurality of program states. | 08-01-2013 |
| 20130198577 | MEMORY, MEMORY SYSTEM, AND ERROR CHECKING AND CORRECTING METHOD FOR MEMORY - A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method. | 08-01-2013 |
| 20130268724 | SSD WITH RAID CONTROLLER AND PROGRAMMING METHOD - A solid state drive (SSD) includes non-volatile memory devices and a RAID controller. Each of the non-volatile memory devices includes a memory cell array having a plurality of physical pages. The RAID controller performs a parity operation on 1st through (N−1)th physical page data to generate Nth physical page data, determines a physical page group including 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices, respectively, such that at least two of the 1st through Nth physical pages have different bit error rates from each other, and stores the 1st through Nth physical page data in the 1st through Nth physical pages, respectively. | 10-10-2013 |
| 20140019675 | NONVOLATLE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME, AND RELATED MEMORY MANAGEMENT, ERASE AND PROGRAMMING METHODS - An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level. | 01-16-2014 |
| 20140136765 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND RELATED READ METHOD - A method of operating a nonvolatile memory device configured to erase a memory block in sub-block units comprises detecting state information of unselected sub-blocks associated with a selected sub-block comprising selected memory cells, adjusting a read bias of the selected memory cells based on the state information, and reading data from the selected memory cells according to the adjusted read bias. The state information indicates a number of the unselected sub-blocks having a programmed state or an erased state. | 05-15-2014 |
| 20140281279 | NONVOLATILE MEMORY DEVICE AND DATA MANAGEMENT METHOD THEREOF - A data management method of a nonvolatile memory device which includes a data cell area and a reference cell area includes selecting shared data from write data input to the memory device; generating reference data based on the shared data; and storing the write data in the data cell area and a first reference area of the reference cell area; and storing the reference data in a second reference area of the reference cell area. | 09-18-2014 |
| 20140281824 | NONVOLATILE MEMORY DEVICE AND DATA WRITE METHOD - A data write method of a nonvolatile memory device is provided which includes receiving write data to be stored in selected memory cells; reading data stored in the selected memory cells; processing the write data according to a plurality of data modulation manners to generate a plurality of modulated data values; calculating the number of flip bits and the number of switching bits when the write data and the plurality of modulated data values are overwritten on the selected memory cells, each flip bit indicating that a logical value of a selected memory cell is reversed and each switching bit indicating that a logical value of a selected memory cell is switched from a first logical value to a second logical value; and selecting one of the write data and the plurality of modulated data values according to calculating the number of flip bits and the number of switching bits. | 09-18-2014 |
| 20150162093 | MEMORY CONTROLLER OPERATING METHOD AND MEMORY SYSTEM INCLUDING MEMORY CONTROLLER - A method of operating a memory controller in a memory system including a nonvolatile memory device includes; erasing memory cells of a target memory block of the non-volatile memory device on a block basis, and then searching for a bad memory cell by a performing an erase verifying operation, comparing a threshold voltage of the bad memory cell to a reference voltage to generate comparison results, and designating as a bad area one of the entire target memory block, and a sub-block of the target memory block in response to the comparison results. | 06-11-2015 |
| 20150199267 | MEMORY CONTROLLER, SYSTEM COMPRISING MEMORY CONTROLLER, AND RELATED METHODS OF OPERATION - A method of operating a memory controller comprises receiving original data from an external source, partitioning the original data into multiple elements of unit data, changing an order of at least one element of unit data to reduce the number of occurrences of a target state among the multiple units of unit data, and controlling a non-volatile memory device to program the multiple elements of unit data having the reduced number of occurrences of the target state. | 07-16-2015 |
| 20150220283 | OPERATING METHOD OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM - An operating method of a nonvolatile memory device which includes receiving a plurality of sub-page data and a write command from an external device; performing a pre-main program operation such that at least one of the plurality of sub-page data is stored in the second plurality of memory cells included in the main region; performing a buffered program operation such that other received sub-page data is stored in the first plurality of memory cells included in the buffer region; and performing a re-main program operation such that the received sub-page data subjected to the buffered program operation at the buffer region is stored in the second plurality of memory cells subjected to the pre-main program operation. | 08-06-2015 |
| 20160093387 | METHOD OF OPERATING A MEMORY SYSTEM HAVING AN ERASE CONTROL UNIT - A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes performing pre-reading a plurality of memory cells connected to a selected word line of the memory block, generating an off cell count based on the pre-reading result, by operation of the erase control unit, comparing the off cell count with a reference value to generate a comparison result, and changing an erase operation condition based on the comparison result, by operation of the nonvolatile memory, and erasing the memory block according to the changed erase operation condition. | 03-31-2016 |
| Patent application number | Description | Published |
|---|
| 20100112774 | Variable Resistance Memory Device and Methods of Forming the Same - A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern. | 05-06-2010 |
| 20110020998 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL ALLOY ELECTRODE - A semiconductor device includes an electrode having a metal silicide layer and a metal alloy layer, and a data storage element formed on the electrode. The metal silicide layer has a concave surface to correspond to a convex surface of the metal alloy layer such that the concave surface of the metal silicide layer and the convex surface of the metal alloy layer form a curved boundary. | 01-27-2011 |
| 20110124174 | METHOD OF FORMING VARIABLE RESISTANCE MEMORY DEVICE - Provided are a method of forming an electrode of a variable resistance memory device and a variable resistance semiconductor memory device using the method. The method includes: forming a heat electrode; forming a variable resistance material layer on the heat electrode; and forming a top electrode on the variable resistance material layer, wherein the heat electrode includes a nitride of a metal whose atomic radius is greater than that of titanium (Ti) and is formed through a thermal chemical vapor deposition (CVD) method without using plasma. | 05-26-2011 |
| 20110186798 | Phase Changeable Memory Devices and Methods of Forming the Same - Phase changeable memory devices are provided including a mold insulating layer on a substrate, the mold insulating layer defining an opening therein. A phase-change material layer is provided in the opening. The phase-change material includes an upper surface that is below a surface of the mold insulating layer. A first electrode is provided in the opening and on the phase-change material layer. A spacer is provided between a sidewall of the mold insulating layer and the phase-change material layer and the first electrode. The upper surface of the first electrode is coplanar with the surface of the mold insulating layer. Related methods are also provided. | 08-04-2011 |
| 20120305884 | VARIABLE RESISTANCE MEMORY DEVICE AND METHODS OF FORMING THE SAME - A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern. | 12-06-2012 |
| 20140124726 | PHASE-CHANGE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Provided are a phase-change memory device and a method of fabricating the same. The device may include memory cells provided at intersections of word lines and bit lines that extend along first and second directions crossing each other, and a mold layer including thermal insulating regions, such as air gaps, that may be provided between the memory cells to separate the memory cells from each other. Each of the memory cells may include a lower electrode electrically connected to the word line to have a first width in the first direction, an upper electrode electrically connected to the bit line to have a second width greater than the first width in the first direction, and a phase-change layer provided between the lower and upper electrodes to have the first width in the first direction. | 05-08-2014 |
| Patent application number | Description | Published |
|---|
| 20080308784 | VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME - Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer. | 12-18-2008 |
| 20090008623 | Methods of fabricating nonvolatile memory device and a nonvolatile memory device - Methods of fabricating a nonvolatile memory device using a resistance material and a nonvolatile memory device are provided. According to example embodiments, a method of fabricating a nonvolatile memory device may include forming at least one semiconductor pattern on a substrate, forming a metal layer on the at least one semiconductor pattern, forming a mixed-phase metal silicide layer, in which at least two phases coexist, by performing at least one heat treatment on the substrate so that the at least one semiconductor pattern may react with the metal layer, and exposing the substrate to an etching gas. | 01-08-2009 |
| 20100093130 | Methods of forming multi-level cell of semiconductor memory - Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided. | 04-15-2010 |
| 20100144138 | METHODS OF FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES FABRICATED USING CONTACT STRUCTURES - Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole. | 06-10-2010 |
| 20100190321 | METHOD OF FABRICATING PHASE-CHANGE MEMORY DEVICE HAVING TiC LAYER - Provided is a method of fabricating a phase-change memory device. The phase-change memory device includes a memory cell having a switching device and a phase change pattern. The method includes; forming a TiC layer on a contact electrically connecting the switching device using a plasma enhanced cyclic chemical vapor deposition (PE-cyclic CVD) process, patterning the TiC layer to form a lower electrode on the contact, and forming the phase-change pattern on the lower electrode. | 07-29-2010 |
| 20100243982 | VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME - Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer. | 09-30-2010 |
| 20110155985 | PHASE CHANGE STRUCTURE, AND PHASE CHANGE MEMORY DEVICE - A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a high aspect ratio structure, and the second phase change material layer pattern may fully fill the high aspect ratio structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material. | 06-30-2011 |
| 20120040508 | Method of Forming Semiconductor Device Having Self-Aligned Plug - A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug. | 02-16-2012 |
| 20120119181 | SEMICONDUCTOR DEVICE INCLUDING BUFFER ELECTRODE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern. | 05-17-2012 |
| 20120231603 | Methods of forming phase change material layers and methods of manufacturing phase change memory devices - A phase change material layer includes a Ge-M-Te (GMT) ternary phase change material, where Ge is germanium, M is a heavy metal, and Te is tellurium. The GMT ternary phase change material may also include a dopant. | 09-13-2012 |
| 20120252187 | Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern. | 10-04-2012 |
| 20120282751 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING FINE PATTERNS - A method of fabricating an integrated circuit device includes forming first and second patterns extending in first and second directions, respectively, on a target layer. The first patterns comprise a metal oxide and/or metal silicate material having an etch selectivity with respect to that of the target layer. The second patterns comprise a material having an etch selectivity with respect to those of the first patterns and the target layer. The target layer is selectively etched using the first patterns and the second patterns as an etch mask to define holes respectively extending through the target layer to expose a layer therebelow. At least one of the first and second patterns is formed using respective mask patterns formed by a photolithographic process, and the at least one of the first and second patterns have a finer pitch than that of the respective mask patterns. | 11-08-2012 |
| 20120305522 | MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME - Memory devices and methods of forming memory devices including forming a plurality of preliminary electrodes, each of the plurality of preliminary electrodes including a protruding region, protruding from a first mold insulating layer, forming a second mold insulating layer on the first mold insulating layer, removing at least a portion of the plurality of preliminary electrodes to form a plurality of openings in the second mold insulating layer and a plurality of lower electrodes, and forming a plurality of memory elements in the plurality of openings. Memory devices and methods of forming memory devices including forming one or more insulating layers on sidewalls of all or part of a plurality of lower electrodes and/or a plurality of memory elements. | 12-06-2012 |
| 20120322223 | METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICES - A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode. | 12-20-2012 |
| 20120326110 | PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern. | 12-27-2012 |
| 20130099190 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A diode may be foamed within a molding layer on a substrate. A conductive buffer pattern having a greater planar area than the diode may be on the diode and molding layer. An electrode structure may be on the conductive buffer pattern. A data storage pattern may be on the electrode structure. One lateral surface of the conductive buffer pattern may be vertically aligned with one lateral surface of the electrode structure. | 04-25-2013 |
| 20130102150 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE HAVING SMALL CONTACT AND RELATED DEVICES - A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode. | 04-25-2013 |
| 20130109148 | METHODS OF FORMING A PATTERN AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME | 05-02-2013 |
| 20130126510 | NON-VOLATILE MEMORY DEVICES HAVING DUAL HEATER CONFIGURATIONS AND METHODS OF FABRICATING THE SAME - A non-volatile memory device includes a data storage structure coupled between first and second conductive lines of the memory device. The data storage structure includes a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked. At least one sidewall surface of the data storage pattern is coplanar with a sidewall surface of the upper heater element thereabove and a sidewall surface of the lower heater element therebelow. Related fabrication methods are also discussed. | 05-23-2013 |
| 20130143380 | METHODS OF FORMING A PHASE CHANGE LAYER AND METHODS OF FABRICATING A PHASE CHANGE MEMORY DEVICE INCLUDING THE SAME - A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a minute structure, and the second phase change material layer pattern may fully fill the minute structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material. | 06-06-2013 |
| 20130256621 | PHASE-CHANGE MEMORY DEVICES - A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern. | 10-03-2013 |
| 20130302966 | Method of Forming Semiconductor Device Having Self-Aligned Plug - A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug. | 11-14-2013 |
| 20130336046 | NON-VOLATILE MEMORY DEVICE HAVING MULTI-LEVEL CELLS AND METHOD OF FORMING THE SAME - A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode. | 12-19-2013 |
| 20140326942 | NON-VOLATILE MEMORY DEVICE HAVING MULTI-LEVEL CELLS AND METHOD OF FORMING THE SAME - A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode. | 11-06-2014 |
| Patent application number | Description | Published |
|---|
| 20110205645 | LENS DRIVING APPARATUS - A method for driving a lens and a lens driving apparatus, the lens driving apparatus including a base in which a guide member is disposed; a lens support member comprising an installation unit disposed on one side thereof to slidingly move along the guide member, wherein at least one lens is mounted in the lens support member; a driving structure configured to move the lens support member and comprising a lead screw; a working member having one portion contacting the driving structure and another portion contacting one side of the installation unit; an elastic member for providing the installation unit with an elastic force; and wherein a predetermined space is disposed between the installation unit and the base, and wherein the installation unit is configured to be moved to the base by a means other than the driving structure. | 08-25-2011 |
| 20120206820 | ZOOM LENS BARREL ASSEMBLY - A zoom lens barrel assembly including: a first zoom ring comprising a first protrusion; a guide ring disposed around the first zoom ring comprising a first guide slot through which the first protrusion passes, and a second guide slot; a second zoom ring comprising a second protrusion, and movable in an axial direction; a first cylinder comprising a guide groove into which the second protrusion inserts, and a third protrusion passing through the second guide slot, and disposed between the first and second zoom rings; a second cylinder disposed around the guide ring comprising a fourth protrusion, a first groove portion into which the first protrusion inserts, and a second groove portion into which the third protrusion inserts, and supporting the first zoom ring and the first cylinder; and an external cylinder disposed around the second cylinder and comprising a third groove portion into which the fourth protrusion inserts. | 08-16-2012 |
| 20120206821 | ZOOM LENS BARREL ASSEMBLY - A zoom lens barrel assembly includes: a zoom ring having a cylindrical shape, and comprising an inlet portion formed in a boundary of one end thereof and a first protrusion; a guide ring disposed around the zoom ring, and comprising a first guide hole through which the first protrusion passes, and movably supporting the zoom ring in an axial direction, and a second guide hole; and a cylinder disposed in the zoom ring, for moving and rotating between a position where the cylinder is accommodated in the zoom ring and a position where the cylinder moves away from the zoom ring in the axial direction, and comprising a second protrusion that passes through the second guide hole, accommodated in the inlet portion at the position where the cylinder is accommodated, and pressing one end of the inlet portion when the cylinder moves away from the zoom ring. | 08-16-2012 |
| 20130335832 | ZOOM LENS BARREL ASSEMBLY - A zoom lens barrel assembly includes: a first zoom ring comprising a first protrusion; a guide ring disposed around the first zoom ring comprising a first guide slot through which the first protrusion passes, and a second guide slot; a second zoom ring comprising a second protrusion, and movable in an axial direction; a first cylinder comprising a guide groove into which the second protrusion inserts, and a third protrusion passing through the second guide slot, and disposed between the first and second zoom rings; a second cylinder disposed around the guide ring comprising a fourth protrusion, a first groove portion into which the first protrusion inserts, and a second groove portion into which the third protrusion inserts, and supporting the first zoom ring and the first cylinder; and an external cylinder disposed around the second cylinder and comprising a third groove portion into which the fourth protrusion inserts. | 12-19-2013 |
| Patent application number | Description | Published |
|---|
| 20130038621 | DISPLAY DEVICE AND DRIVING METHOD THEREOF - The present invention provides a display device with reduced power consumption and that reduces changes in luminance, and perceptibility of flicker, and a driving method thereof. A display device according to an exemplary embodiment comprises: a display panel configured to display a still image and a motion picture; a signal controller configured to control signals for driving the display panel; and a graphics processing unit configured to transmit input image data to the signal controller, wherein the signal controller comprises a frame memory configured to store the input image data, and the display panel is driven at a first frequency when the motion picture is displayed and the display panel is driven at a second frequency that is lower than the first frequency when the still image is displayed. | 02-14-2013 |
| 20150179131 | TIMING CONTROLLER AND DISPLAY APPARATUS HAVING THE SAME - A timing controller includes: a top voltage generator configured to output first to third top voltages; a bottom voltage generator configured to output first to third bottom voltages; a first transmitting part configured to output a first data signal for a first data driving chip, based on the first top and bottom voltages; a second transmitting part configured to output a second data signal for a second data driving chip based on the second top and bottom voltages; and a third transmitting part configured to output a third data signal for a third data driving chip based on the third top and bottom voltages, where one of the first to third top voltages is different from another of the first to third top voltages, and one of the first to third bottom voltages is different from another of the first to third bottom voltages. | 06-25-2015 |
| 20150302812 | LIQUID CRYSTAL DISPLAY APPARATUS AND DRIVING METHOD THEREOF - A liquid crystal display device includes a liquid crystal panel which includes gate lines, data lines crossing the gate lines, and pixels connected to the gate lines and the data lines; a timing controller for receiving a control signal and image data and for generating a gate control signal and a data control signal; a gate driver for generating a gate signal based on the gate control signal and outputting the gate signal to the gate lines; and a data driver for performing data conversion on the image data based on the data control signal and outputting a conversion result to the data lines, wherein the timing controller analyzes the image data frame by frame data and applies two or more inversion driving techniques to frame data. | 10-22-2015 |
| 20150371609 | DISPLAY DEVICE AND DRIVING METHOD THEREOF - The present invention provides a display device with reduced power consumption and that reduces changes in luminance, and perceptibility of flicker, and a driving method thereof. A display device according to an exemplary embodiment comprises: a display panel configured to display a still image and a motion picture; a signal controller configured to control signals for driving the display panel; and a graphics processing unit configured to transmit input image data to the signal controller, wherein the signal controller comprises a frame memory configured to store the input image data, and the display panel is driven at a first frequency when the motion picture is displayed and the display panel is driven at a second frequency that is lower than the first frequency when the still image is displayed. | 12-24-2015 |
| 20160049123 | METHOD OF DRIVING A DISPLAY PANEL AND DISPLAY APPARATUS PERFORMING THE SAME - A method of driving a display panel includes compensating first pixel data corresponding to a first pixel of a plurality of pixels in the display panel based on at least one of a first decision, a second decision, or a third decision and generating a first data voltage corresponding to the compensated first pixel data. The first data voltage is applied to the first pixel through a data line. The first decision includes determining, based on a position of the first pixel, whether compensation for the first pixel data is required. The second decision includes determining, based on previous subpixel data and present subpixel data for the first pixel, whether the compensation for the first pixel data is required. The third decision includes determining whether the first pixel data complies with a compensation avoidance condition. | 02-18-2016 |
| Patent application number | Description | Published |
|---|
| 20090102727 | Mobile terminal having additional antenna pattern in main body - The present invention relates to a mobile terminal having an antenna pattern in a main body of the mobile terminal. The mobile terminal includes: a main body having a feed point; a first antenna disposed in the main body, and a second antenna; wherein the second antenna is connected to the first antenna when the first antenna is retracted into the main body. According to the present invention, a digital broadcast signal can be received efficiently without extending an antenna to the outside of a main body of a mobile terminal. Further, damage to an antenna and wear of an antenna connection part are decreased. | 04-23-2009 |
| 20110155445 | SHIELD CAN OF MOBILE TERMINAL - A shield can of a mobile terminal is provided. The shield can of the mobile terminal includes: at least one shield can installed in a main circuit board of the mobile terminal, and at least one separation wall formed between electronic elements in which electromagnetic interference occurs within the shield can. Hence, shield ability can be improved and simplified manufacturing process of the separation wall can reduce cost. | 06-30-2011 |
| 20110156967 | TOUCH SCREEN PANEL ANTENNA OF MOBILE TERMINAL - A touch screen panel (TSP) antenna of a mobile terminal is provided. The TSP antenna includes an ITO film stacked in a TSP, an upper electrode line, a lower electrode line, a left electrode line, and a right electrode line formed at an upper or lower surface of the ITO film, an external surface, and an antenna pattern formed in at least one of an upper surface, a lower surface, a left surface, and a right surface of the external surface. | 06-30-2011 |
| 20140092578 | SHIELD CAN OF MOBILE TERMINAL - A shield can of a mobile terminal is provided. The shield can of the mobile terminal includes: at least one shield can installed in a main circuit board of the mobile terminal, and at least one separation wall formed between electronic elements in which electromagnetic interference occurs within the shield can. Hence, shield ability can be improved and simplified manufacturing process of the separation wall can reduce cost. | 04-03-2014 |
| 20150216091 | SHIELD CAN OF MOBILE TERMINAL - A shield can of a mobile terminal is provided. The shield can of the mobile terminal includes: at least one shield can installed in a main circuit board of the mobile terminal, and at least one separation wall formed between electronic elements in which electromagnetic interference occurs within the shield can. Hence, shield ability can be improved and simplified manufacturing process of the separation wall can reduce cost. | 07-30-2015 |
| Patent application number | Description | Published |
|---|
| 20090140075 | DEVICE FOR REMOVABLY COUPLING DISPOSABLE NOZZLE TIP FOR BIDET - Disclosed herein is a device for removably coupling a disposable nozzle tip for a bidet. The device includes a nozzle, a nozzle tip, a guide cover, and a removable coupling unit. The nozzle has a nozzle body through which a washing-water guide hole passes, and a coupling hole. The nozzle tip has a coupling protrusion removably inserted into the coupling hole, and a jet hole to spray washing water. The guide cover is secured to a bottom of the nozzle tip in such a way as to be positioned under the jet hole, and guides the washing water to the jet hole. The removable coupling unit includes external threads formed in an outer circumference of the coupling protrusion, and internal threads formed in an inner circumference of the coupling hole. Further, the device includes stoppers comprising a pair of a protrusion and a hole, or a pair of protrusions, provided on the nozzle and the nozzle tip in such a way as to be symmetric with respect to each other, and preventing the nozzle tip from excessively rotating relative to the nozzle. The device provides a clean nozzle tip, thus allowing the genital and anal areas to be hygienically washed using washing water, and simplifies the structure of the nozzle tip, thus facilitating a mounting and detaching operation, and includes stoppers, thus preventing the nozzle and the nozzle tip from being damaged. | 06-04-2009 |
| 20110010834 | DEVICE FOR REMOVABLY COUPLING DISPOSABLE NOZZLE TIP FOR BIDET - Disclosed herein is a device for removably coupling a disposable nozzle tip for a bidet. The device includes a nozzle, a nozzle tip, a guide cover, and a removable coupling unit. The nozzle has a nozzle body through which a washing-water guide hole passes, and a coupling hole. The nozzle tip has a coupling protrusion removably inserted into the coupling hole, and a jet hole to spray washing water. The guide cover is secured to a bottom of the nozzle tip in such a way as to be positioned under the jet hole, and guides the washing water to the jet hole. The removable coupling unit includes external threads formed in an outer circumference of the coupling protrusion, and internal threads formed in an inner circumference of the coupling hole. Further, the device includes stoppers comprising a pair of a protrusion and a hole, or a pair of protrusions, provided on the nozzle and the nozzle tip in such a way as to be symmetric with respect to each other, and preventing the nozzle tip from excessively rotating relative to the nozzle. The device provides a clean nozzle tip, thus allowing the genital and anal areas to be hygienically washed using washing water, and simplifies the structure of the nozzle tip, thus facilitating a mounting and detaching operation, and includes stoppers, thus preventing the nozzle and the nozzle tip from being damaged. | 01-20-2011 |
| Patent application number | Description | Published |
|---|
| 20110195550 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target. | 08-11-2011 |
| 20110201202 | METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device, the method including providing a patternable layer; forming a plurality of first photoresist layer patterns on the patternable layer; forming an interfacial layer on the patternable layer and the plurality of first photoresist layer patterns; forming a planarization layer on the interfacial layer; forming a plurality of second photoresist layer patterns on the planarization layer; forming a plurality of planarization layer patterns using the plurality of second photoresist layer patterns; and forming a plurality of layer patterns using the plurality of planarization layer patterns and the plurality of first photoresist layer patterns. | 08-18-2011 |
| 20110256700 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device capable of simplifying a fabrication process is provided. The method includes providing a substrate on which first and second regions are defined, forming an interlayer insulating film including first and second trenches on the substrate, the first and second trenches being formed in the first and second regions, respectively, forming a work function adjusting metal film on an upper surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench, forming a mask film on the interlayer insulating film to fill in the first and second trenches, the mask film including a developable material, forming a mask pattern by developing the mask film, the mask pattern exposing the work function adjusting metal film formed in the first region, removing the work function adjusting metal film formed in the first region by using the mask pattern, removing the mask pattern, and forming a first metal gate in the first trench and a second metal gate in the second trench. | 10-20-2011 |
| 20110312152 | Methods of Fabricating Integrated Circuit Devices Using Selective Etching Techniques that Account for Etching Distance Variations - Methods of fabricating integrated circuit devices include forming an integrated circuit capacitor on a substrate. This integrated circuit capacitor includes a lower capacitor electrode, a capacitor dielectric region on the lower capacitor electrode and an upper capacitor electrode on the capacitor dielectric region. The upper capacitor electrode has a smaller surface area relative to the lower capacitor electrode. An interlayer insulating layer is formed on the integrated circuit capacitor. This interlayer insulating layer is polished to have a planarized surface thereon that is spaced from an upper surface of the upper capacitor electrode by a first distance and spaced from an upper surface of the lower capacitor electrode by a second distance greater than the first distance. A step is performed to selectively etch first and second via holes of unequal size in the interlayer insulating layer to expose the upper surface of the lower capacitor electrode and the upper surface of the upper capacitor electrode, respectively. This etching step is performed using an etching process that concurrently etches portions of the interlayer insulating layer associated with the first via hole at a faster rate than portions of the interlayer insulating layer associated with the second via hole, which is larger than the first via hole. | 12-22-2011 |
| 20130023127 | METHOD OF FORMING A CONTACT HOLE AND APPARATUS FOR PERFORMING THE SAME - A method of forming a contact hole includes loading a substrate into a plasma chamber, the substrate including an etch stop layer, an insulation interlayer, a mask layer and a photoresist pattern sequentially disposed thereon, applying a DC voltage to an upper electrode and applying a first high frequency power and a second high frequency power to a lower electrode to generate plasma in the chamber, the first frequency power and second high frequency powers having different frequency levels, supplying a reaction gas to the chamber to etch the mask layer and the insulation interlayer, wherein the chamber is maintained at a temperature of 100° C. to 200° C.; and etching the etch stop layer to form a contact hole | 01-24-2013 |
| 20140103405 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method is provided for fabricating a semiconductor device that includes: forming a gate pattern on a substrate; forming a source/drain in the vicinity of the gate pattern; forming an etch stop film, which covers the gate pattern and the source/drain, on the substrate; forming an interlayer insulating film on the etch stop film; forming a shared contact hole that exposes the gate pattern and the source/drain by etching the interlayer insulating film, wherein a polymer is generated in the shared contact hole a process of etching the interlayer insulating film; removing the polymer by performing etching using hydrogen gas, nitrogen gas or a mixture of hydrogen and nitrogen before etching the etch stop film; and etching the etch stop film. | 04-17-2014 |
