Patent application number | Description | Published |
20160062213 | CAMERA FEATURES OF AN ELECTRONIC DEVICE - An electronic device having a securing member for a camera module is disclosed. The securing member may include several flexible spring elements extending around the camera module to maintain the position of the camera module during an assembly process of the electronic device. The securing member and the housing may be made from an electrically conductive material or materials. In this manner, the securing member may further provide the camera module with an electrical ground to prevent excessive electric charge within the camera module. In some embodiments, an alignment member is positioned on the housing and aligns the camera module and/or securing member with an aperture of the housing. | 03-03-2016 |
20160064810 | FLEXIBLE SHOCK ABSORBING CONNECTIONS WITHIN A MOBILE COMPUTING DEVICE - The subject matter of the disclosure relates to connectors for antenna feed assemblies and display coupling components of a mobile device. The flexible connectors can be configured with a flexible spring connector component that couples a mobile device antenna to a main logic board of the mobile device within a housing of the mobile device such that the flexible connector can withstand a drop event, while at the same providing for an in-line inductance as part of an antenna-defined design requirement. The display of the mobile device can be coupled to a housing of the mobile device using a pin-screw arrangement that allows the display to controllably shift in the X-direction and the Y-direction, while only being purposefully constrained in the Z-direction (with reference to a 3-dimensional graph having X, Y, and Z axes). This configuration can prevent the display from being pulled out of alignment during a drop event. | 03-03-2016 |
20160072996 | DUAL SHOT STROBE LENS AND FLEX AND STIFFENER FEATURES OF A CAMERA - An electronic device having a lens and a lens retaining member is disclosed. The lens and the lens retaining member may both be molded in a single mold cavity. However, the lens includes a first material that is clear and translucent, while the lens retaining member includes a second material that is opaque. The lens retaining member may include an alignment such that the lens and lens retaining member, when secured to a flexible circuit, may self-align with a window. The window allows a light source to emit light while the lens retaining member blocks or reflects light. In another embodiment, a container having a first member and a second member may be positioned around a camera module. The container may act as an EMI shield for the camera module. | 03-10-2016 |
Patent application number | Description | Published |
20090240860 | Lock Mechanism to Enable Atomic Updates to Shared Memory - A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location. | 09-24-2009 |
20090240895 | SYSTEMS AND METHODS FOR COALESCING MEMORY ACCESSES OF PARALLEL THREADS - One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data. When all the memory access requests associated with a particular PRT entry are complete, the core interface satisfies the corresponding application request and frees the PRT entry. | 09-24-2009 |
20090240931 | Indirect Function Call Instructions in a Synchronous Parallel Thread Processor - An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches. | 09-24-2009 |
20110074802 | Architecture and Instructions for Accessing Multi-Dimensional Formatted Surface Memory - One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions. | 03-31-2011 |
20110078417 | COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS - One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread. | 03-31-2011 |
20120036329 | LOCK MECHANISM TO ENABLE ATOMIC UPDATES TO SHARED MEMORY - A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location. | 02-09-2012 |
20120239909 | SYSTEMS AND METHODS FOR VOTING AMONG PARALLEL THREADS - One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance. | 09-20-2012 |
20130138926 | INDIRECT FUNCTION CALL INSTRUCTIONS IN A SYNCHRONOUS PARALLEL THREAD PROCESSOR - An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches. | 05-30-2013 |
20140019724 | COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS - One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread. | 01-16-2014 |