Patent application number | Description | Published |
20080224773 | Digital input class-D amplifier - A digital input class-D amplifier includes a decoder which outputs a plurality of lines of time-series digital signals having a density of 1 or 0 conforming to an input digital signal, an error integrator which integrates a difference between a drive waveform to be applied to a load and a sum of the plurality of lines of time-series digital signals output from the decoder, and a modulation circuit which generates a pulse modulated with a pulse width or a pulse density based on a result of integration performed by the error integrator. The load is driven in accordance with the pulse generated by the modulation circuit. | 09-18-2008 |
20090027121 | Class D amplifier circuit - A pulse monitor circuit detects the presence or non-presence of the output pulses output from an output stage circuit. The pulse monitor circuit outputs an up signal to the up/down counter when the output pulses do not exist at all and outputs a down signal to the up/down counter when the output pulses exist. The up/down counter outputs a signal for increasing the delay amount of a delay amount variable circuit when a count value is large, that is, when the output pulses disappear. In contrast, when the count value is small, that is, when the output pulses exist, the counter outputs the signal for reducing the delay amount of the delay amount variable circuit. | 01-29-2009 |
20090102516 | Comparator - A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors. | 04-23-2009 |
20100117730 | D/A converter circuit and digital input class-D amplifier - The present invention provides a D/A converter circuit which enables D/A conversion with a high precision and can prevent occurrence of a limit cycle component in the case where an input signal is low, and can also prevent the effect of dither signal from occurring in an analog signal which is a D/A conversion result. | 05-13-2010 |
20100164590 | SEMICONDUCTOR INTEGRATED CIRCUIT - An N-channel transistor is provided as a switch between a high potential power line and a low potential power line. A high-pass filter is constituted by a capacitor and a resistor. When a voltage between the high potential power line and the low potential power line is started to oscillate by a switching operation, the high-pass filter causes a high-pass component thereof to pass, thereby turning ON the N-channel transistor to reduce a ringing. | 07-01-2010 |
20100244958 | Class D amplifier circuit - A class D amplifier circuit includes a signal generation section that generates a first pulse width modulation signal and a second pulse width modulation signal based on an input signal. When a level of the input signal is zero, the signal generation section generates: the first pulse width modulation signal having a repeated first wide-width pulse signal portion, which has a wide width and a repeated first narrow-width pulse signal portion, which has a narrow width which is narrower than the wide width of the first wide-width pulse signal; and the second pulse width modulation signal having a repeated second narrow-width pulse signal portion, which has a narrow width and a repeated second wide-width pulse signal portion, which has a wide width which is wider than the narrow width of the second narrow-width pulse signal portion. A rising point in time of the second narrow-width pulse signal portion occurs after a rising point in time of the first wide-width pulse signal portion and a falling point in time of the second narrow-width pulse signal portion occurs before a falling point in time of the first wide-width pulse signal portion. A rising point in time of the first narrow-width pulse signal portion occurs after a rising point in time of the second wide-width pulse signal portion and a falling point in time of the first narrow-width pulse signal portion occurs before a falling point in time of the second wide-width pulse signal portion. | 09-30-2010 |
20110006843 | Offset voltage correction circuit and class D amplifier - A class D amplifier includes an input unit that inputs an input signal and an integrator which includes a differential operational amplifier having an offset voltage correction function. The integrator integrates the input signal input. A pulse-width modulator modulates the integration result of the integrator to generate a pulse signal having a pulse width reflective of the integration result. An output unit outputs the pulse signal. A feedback unit superimposes a signal output from the output unit on the input signal and feeds back the superimposed signal to the integrator. An input controller selectively set the input unit to a state where no signal is input. An output controller sets a voltage of an output from the feedback unit to a constant voltage. | 01-13-2011 |
20110140941 | Voltage adder circuit and D/A converter circuit - A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit. | 06-16-2011 |
20110148375 | Power amplifying circuit, DC-DC converter, peak holding circuit, and output voltage control circuit including the peak holding circuit - A power amplifying circuit includes a first field effect transistor and a second field effect transistor that are connected in series, are interposed between a high potential power line and a low potential power line, and drive a load; a predriver that generates, in response to an input signal, gate voltages applied to the first field effect transistor and the second field effect transistor respectively; and a variable power source that supplies source voltages to the high potential power line and the low potential power line respectively, and is configured to control the source voltages. | 06-23-2011 |
20120068675 | Voltage generation circuit - A voltage generation circuit includes a voltage detection circuit that generates a detection voltage according to an output voltage, a reference voltage generation circuit that generates a reference voltage which changes periodically, a comparison circuit that generates a control signal according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses each having a pulse width according to the detection voltage are sequentially appeared in the control signal, and a driving pulse generation circuit that generates a driving pulse corresponding to the control pulse and supplies the generated driving pulse to a transistor connected to a DC power source when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width. | 03-22-2012 |
20120068676 | VOLTAGE GENERATION CIRCUIT - A voltage generation circuit includes a voltage detection circuit that generates a detection voltage according to an output voltage, a reference voltage generation circuit that generates a reference voltage which changes periodically, a comparison circuit that generates a control signal according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses each having a pulse width according to the detection voltage are sequentially appeared in the control signal, and a driving pulse generation circuit that generates a driving pulse corresponding to the control pulse and supplies the generated driving pulse to a transistor connected to a DC power source when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width. | 03-22-2012 |