Patent application number | Description | Published |
20080198659 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged therein; and a sense amplifier circuit configured to read data of the memory cell array, wherein a comparison operation is performed between read out data from the memory cell array and externally supplied expectance data in the sense amplifier circuit. | 08-21-2008 |
20080219058 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 09-11-2008 |
20080239822 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell. | 10-02-2008 |
20080285345 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 11-20-2008 |
20080304319 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 12-11-2008 |
20080313387 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF READING DATA RELIABLY - A control unit reads data from a plurality of memory cells connected to one of the word lines in a read operation at a first level CR generated by a voltage generator circuit and in a read operation at a second level CR−x and finds the number of cells included between the first level and the second level from the data and, if the number is equal to or smaller than a specified value, determines the result of the read operation at the first level to be read data. | 12-18-2008 |
20090016117 | HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE - A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing. | 01-15-2009 |
20090034329 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SUPPRESSING PEAK CURRENT - A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule. | 02-05-2009 |
20090067236 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory device includes a control circuit which controls a semiconductor region, a first bit line, a second bit line and a source line. The control circuit is comprised of means for making the first bit line floating, after pre-charging the first bit line to a first potential, means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state, and means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential. | 03-12-2009 |
20090067245 | SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH MOS TRANSISTOR HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA WRITE METHOD OF NAND FLASH MEMORY - A semiconductor memory device includes a memory cell group, a selection transistor, a page buffer, and a row decoder. The memory cell group includes memory cell transistors connected in series. The selection transistor is connected to the memory cell transistor. The page buffer is adopted to apply first and second voltages to the bit lines connected to the memory cell transistors in which the “0” data and “1” data is to be programmed respectively, when the selection transistor is turned on, in a write operation. The page buffer is adopted to put the bit line into electrically floating after the first voltage and the second voltage are applied. The row decoder is adopted to apply a third voltage to a semiconductor layer on which the memory cell transistors are formed, and apply a program voltage to the selected word line when the bit line is in the electrically floating. | 03-12-2009 |
20090067255 | NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL FOR STORING MULTILEVEL DATA HAVING TWO OR MORE VALUES - A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage. | 03-12-2009 |
20090073766 | SEMICONDUCTOR MEMORY DEVICE WHICH GENERATES VOLTAGES CORRESPONDING TO A PLURALITY OF THRESHOLD VOLTAGES - A memory cell MC stores a plurality of bits of data using threshold levels | 03-19-2009 |
20090135648 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTILEVEL DATA - In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell. | 05-28-2009 |
20090141553 | SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line. | 06-04-2009 |
20090154239 | NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS - A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association with 2 | 06-18-2009 |
20090154252 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME - In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage. | 06-18-2009 |
20090168515 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 07-02-2009 |
20090168522 | SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ECC EFFICIENCY - Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells. | 07-02-2009 |
20090190399 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CORRECTING A READ LEVEL PROPERLY - In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level. | 07-30-2009 |
20090201726 | NON-VOLATILE SEMICONDUCTOR STORAGE SYSTEM - In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value. | 08-13-2009 |
20090285029 | HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE - A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing. | 11-19-2009 |
20090303791 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 12-10-2009 |
20090316479 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF LOWERING A WRITE VOLTAGE - A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with input data. The control circuit supplies a first voltage to a word line of a selected cell in a write operation, and supplies a second voltage to at least one word line adjacent to the selected cell. Thereafter, the control circuit changes a voltage of the at least one word line adjacent to the selected cell from the second voltage to a third voltage (second voltage12-24-2009 | |
20100091570 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 04-15-2010 |
20100097864 | SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 04-22-2010 |
20100118605 | SEMICONDUCTOR STORAGE DEVICE ADAPTED TO PREVENT ERRONEOUS WRITING TO NON-SELECTED MEMORY CELLS - A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation. | 05-13-2010 |
20100124109 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTI LEVEL DATA - A memory cell array is configured so that a plurality of memory cells which are connected to a word line and a bit line store one value out of n values (n is a natural number of 2 or more) in one memory cell and are arranged in a matrix. A control circuit controls electronic potentials of the word line and the bit line in response to input data to write data in the memory cells. When writing data in the first memory cell of the memory cell array, the control circuit varies a writing level on the basis of writing data to write in a second memory cell adjacent to the first memory cell. | 05-20-2010 |
20100142270 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM STORING MULTILEVEL DATA - A first memory cell stores data of k bits in one cell. A second memory cell stores data of h bits (h06-10-2010 | |
20100142271 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING A SHIFT OF THRESHOLD VOLTAGE - A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels. | 06-10-2010 |
20100214852 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 08-26-2010 |
20100277980 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 11-04-2010 |
20100329006 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MEMORIZING MULTIVALUED DATA - In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2 | 12-30-2010 |
20110013456 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE - According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. | 01-20-2011 |
20110019477 | NAND TYPE FLASH MEMORY - According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block. | 01-27-2011 |
20110058416 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SUPPRESSING PEAK CURRENT - A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule. | 03-10-2011 |
20110069545 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell. | 03-24-2011 |
20110096605 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell. | 04-28-2011 |
20110141811 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region. | 06-16-2011 |
20110164458 | HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE - A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing. | 07-07-2011 |
20110170347 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ACCURATE READING EVEN WHEN ERASURE LEVEL CHANGES - According to one embodiment, a semiconductor memory device includes a memory cell array and a controller. The memory cell array includes first, second, and third memory cells each of which stores k-bit data (where k is a natural number not smaller than 1). The first and second memory cells are adjacent to each other, and the second and third memory cells are adjacent to each other. Data is stored into the memory cells in an order of the first, second, and third memory cells. When reading data from the second memory cells, the controller reads data from the first and third memory cells, and changes read conditions for the second memory cell in accordance with the read data. | 07-14-2011 |
20110170350 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 07-14-2011 |
20110176362 | SEMICONDUCTOR STORAGE DEVICE CAPABLE OF REDUCING ERASURE TIME - According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The distribution state of the threshold voltages of the memory cells is monitored by the read operation, the distribution state of the threshold voltages of the memory cells after the soft erasure is monitored, and an erase voltage is set based on the monitored results. Thus, the erase voltage can be precisely set without depending on the threshold voltage distribution of the memory cell before the erasure. | 07-21-2011 |
20110238889 | SEMICONDUCTOR MEMORY DEVICE FROM WHICH DATA CAN BE READ AT LOW POWER - According to one embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array is composed of a plurality of memory cells arranged in a matrix pattern. The control circuit sets a first flag data in a second memory cell in order to write data to a plurality of first memory cells of memory cell array, the second memory cell having been selected at the same time as the first memory cells, determines whether the first flag data is set in the second memory cell before data is read from the first memory cells, and reads no data from the first memory cells and outputs data of first logic level if the first flag data is not set in the second memory cell, and reads data from the first memory cells if the first flag data is set in the second memory cell. | 09-29-2011 |
20110242890 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining | 10-06-2011 |
20110242903 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENIN ERASE TIME - In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage. | 10-06-2011 |
20110261619 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF LOWERING A WRITE VOLTAGE - A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with input data. The control circuit supplies a first voltage to a word line of a selected cell in a write operation, and supplies a second voltage to at least one word line adjacent to the selected cell. Thereafter, the control circuit changes a voltage of the at least one word line adjacent to the selected cell from the second voltage to a third voltage (second voltage10-27-2011 | |
20120044764 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command. | 02-23-2012 |
20120092929 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 04-19-2012 |
20120113717 | SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ECC EFFICIENCY - Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells. | 05-10-2012 |
20120147670 | SEMICONDUCTOR STORAGE DEVICE ADAPTED TO PREVENT ERRONEOUS WRITING TO NON-SELECTED MEMORY CELLS - A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation. | 06-14-2012 |
20120163078 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SUPPRESSING PEAK CURRENT - A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule. | 06-28-2012 |
20120163091 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 06-28-2012 |
20120163112 | SEMICONDUCTOR STORAGE SYSTEM CAPABLE OF SUPPRESSING PEAK CURRENT - According to one embodiment, in a semiconductor storage system, the power supply wiring is connected to a first semiconductor storage device, and second semiconductor storage device as a common connection, and supplies power to the first and second semiconductor storage devices. A voltage detection circuit is provided in each of the first and second semiconductor storage devices. Each of the voltage detection circuits detects a power supply voltage of the power supply wiring. A control circuit is provided in each of the first and second semiconductor storage devices. When lowering of the power supply voltage is detected by a corresponding voltage detection circuit, each of the control circuits does not shift the operation of the first or second semiconductor storage device to the next operation until the power supply voltage is restored. | 06-28-2012 |
20120182800 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING A SHIFT OF THRESHOLD VOLTAGE - A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels. | 07-19-2012 |
20120201079 | SEMICONDUCTOR MEMORY DEVICE IN WHICH CAPACITANCE BETWEEN BIT LINES IS REDUCED, AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first bit lines and second bit lines are arranged in different layers. | 08-09-2012 |
20120206977 | SEMICONDUCTOR MEMORY SYSTEM CAPABLE OF SUPPRESSING CONSUMPTION CURRENT - According to one embodiment, a semiconductor memory system includes a first semiconductor memory device, a second semiconductor memory device, and a wiring line. The wiring line is connected between the first semiconductor memory device and the second semiconductor memory device. When one of the first and second semiconductor memory devices discharges electric charge, the other of the first and second semiconductor memory devices receives the discharged electric charge through the wiring line. | 08-16-2012 |
20120235218 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well. | 09-20-2012 |
20120268978 | SEMICONDUCTOR MEMORY DEVICE IN WHICH CAPACITANCE BETWEEN BIT LINES IS REDUCED, AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first bit lines and second bit lines are arranged in different layers. | 10-25-2012 |
20120294089 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MEMORIZING MULTIVALUED DATA - In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2 | 11-22-2012 |
20120320682 | Semiconductor Memory System Including A Plurality Of Semiconductor Memory Devices - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 12-20-2012 |
20130003461 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE - According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. | 01-03-2013 |
20130039126 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of | 02-14-2013 |
20130141970 | HIGH-SPEED READABLE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell. | 06-06-2013 |
20130142324 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 06-06-2013 |
20130142325 | MEMORY - According to one embodiment, a memory includes a first storage region capable of storing first key (NKey) information, and secret identification information (SecretID) unique to the authenticate, reading and writing data from and to the first storage region from an outside of the authenticatee being inhibited at least after the authenticatee is shipped. | 06-06-2013 |
20130142333 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a device includes a storage and an authenticator. The storage includes a first area, a second area and a third area. The first area stores NKey and SecretID, the second area stores index information. E-SecretID is generated by SecretID. The third area stores FKB including information generated by FKey. The authenticator authenticates the external device. HKey is generated by an AES encryption calculating using NKey and HC. A SKey is generated by an AES encryption process using HKey and RN. A one-way conversion calculating is performed. E-SecretID, FKB and Oneway-ID are output to the external device. The index information is read from the second area. | 06-06-2013 |
20130145083 | Semiconductor Memory Device - According to one embodiment, a semiconductor memory device includes a memory which comprises an area accessible from outside and a confidential information area storing confidential information and a set flag. A controller reads the flag from the memory when instructed to erase data in the confidential information area, determines whether the flag is set, erases data in the confidential information area when the flag is clear, and abandons process requested by the data erase instruction when the flag is set. An authenticator uses data in the confidential information area to execute operation for authentication. | 06-06-2013 |
20130145162 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, a device includes first and second data generator, a one-way function processor, and a data output interface. The first data generator generates a second key by encrypting a host constant with a first key in AES operation. The second data generator generates a session key by encrypting a random number with a second key in AES operation. The one-way function processor generates authentication information by processing secret identification information with the session key in one-way function operation. The data output interface outputs the encrypted secret identification information, a family key block, and the authentication information to outside of the device. | 06-06-2013 |
20130145164 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a device includes a first memory area to store a first key. A second memory area stores encrypted secret identification (ID) information generated from secret ID information with a family key. A third memory area stores a family key block including data generated from the family key with an ID key. An authentication module performs authentication. A second key is generated from a first number with the first key, a session key is generated from a random number with the second key, and authentication information is generated from the secret ID information with the session key. The encrypted secret ID information, family key block and the authentication information is output. | 06-06-2013 |
20130148424 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 06-13-2013 |
20130238931 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE HAVING ENCRYPTING ARITHMETIC DEVICE - According to one embodiment, a nonvolatile semiconductor storage device includes an encrypting circuit for operating in a predetermined encrypting system, a memory cell array preliminarily storing complementary data to be used in the operation, and a page buffer having a first region for storing the data being read out from the memory cell array, and a second region used when executing the operation. | 09-12-2013 |
20130286730 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTILEVEL DATA - According to one embodiment, a semiconductor memory device includes a memory cell, a flag memory cell for a flag, a dummy cell and a controller. The flag memory cell is selected at the same time as the memory cell. The dummy cell is selected at the same time as the memory cell and the flag memory cell. The controller controls write and read of the memory cell, the flag memory cell and the dummy cell. Data is written also in the dummy cell which neighbors the flag cell. | 10-31-2013 |
20140010015 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command. | 01-09-2014 |
20140029337 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 01-30-2014 |
20140063973 | SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 03-06-2014 |
20140071754 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction. | 03-13-2014 |
20140086411 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a device includes a storage and an authenticator. The storage includes a first area, a second area and a third area. The first area stores NKey and SecretID, the second area stores index information. E-SecretID is generated by SecretID. The third area stores FKB including information generated by FKey. The authenticator authenticates the external device. HKey is generated by an AES encryption calculating using NKey and HC. A SKey is generated by an AES encryption process using HKey and RN. A one-way conversion calculating is performed. E-SecretID, FKB and Oneway-ID are output to the external device. The index information is read from the second area. | 03-27-2014 |
20140185383 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first NAND string and a second NAND string are connected to a bit line. One of the first and second NAND strings is selected by first to fourth select memory cells. At the write time, data is written in a first memory cell of the first NAND string selected by of the first to fourth select memory cells, then data is written in a second memory cell of the second NAND string selected at the same time as the first memory cell, data is written in a third memory cell adjacent to the first memory cell of the first NAND string and finally data is written in a fourth memory cell of the second NAND string selected at the same time as the third memory cell. | 07-03-2014 |
20140233309 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the bit line. In a read of k−1 levels (k≦n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing. | 08-21-2014 |
20140233312 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of | 08-21-2014 |
20140237244 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-21-2014 |
20140237245 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-21-2014 |
20140237249 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-21-2014 |
20140237258 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-21-2014 |
20140237263 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM USING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and an encryption arithmetic module. The memory cell array includes a first storage area and a second storage area. The first storage area is inhibited from being written into and read from and stores secret key data. The second storage area is inhibited from being written into and permitted to be read from and stores encrypted key data and an expected value. The encryption arithmetic module carries out an authentication operation based on the secret key data and message data. The expected value is the result of carrying out the authentication operation. | 08-21-2014 |
20140241527 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-28-2014 |
20140245010 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-28-2014 |
20140245011 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-28-2014 |
20140245023 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-28-2014 |
20140245024 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information. | 08-28-2014 |
20150071004 | SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 03-12-2015 |