Patent application number | Description | Published |
20110019470 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, in which a multi-bit region including multi-bit memory cells that store data of two or more bits and a region including memory cells that store data of bits that are less than the bits of the data stored in the multi-bit memory cells are installed, is provided, which can perform a high-speed writing and lengthen the life span of the product without increasing the storage capacity of the region of the memory cells storing the data of bits that are less than the bits of the data in the multi-bit memory cells. The semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i01-27-2011 | |
20110211395 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier. | 09-01-2011 |
20130028019 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i01-31-2013 | |
Patent application number | Description | Published |
20120230115 | HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE - A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing. | 09-13-2012 |
20150269992 | NONVOLATILE MEMORY AND WRITING METHOD - According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region. | 09-24-2015 |
20150302920 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell. | 10-22-2015 |