Patent application number | Description | Published |
20100161886 | Architecture for Address Mapping of Managed Non-Volatile Memory - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 06-24-2010 |
20100287329 | Partial Page Operations for Non-Volatile Memory Systems - A read command initiates reads of pages or portions of pages of non-volatile memory using a memory address that specifies a row, column and length. A host controller can use the read command with a read operation or status request. In some implementations, the memory address further specifies a die or plane and a block. | 11-11-2010 |
20100287353 | Multipage Preparation Commands for Non-Volatile Memory Systems - Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation. | 11-11-2010 |
20100287446 | Low Latency Read Operation for Managed Non-Volatile Memory - In a memory system, a host controller is coupled to a non-volatile memory (NVM) package (e.g., NAND device). The host controller sends a read command to the NVM package requesting a low latency read operation. Responsive to the read command, a controller in the NVM package retrieves the data and sends the data to an ECC engine for correcting. Following the read command, the host controller sends a read status request command to the controller in the NVM package. Responsive to the read status request, the controller sends a status report to the host controller indicating that some or all of the data is available for transfer to the host controller. Responsive to the report, the host controller transfers the data. An underrun status can be determined to indicate that uncorrected data had been transferred to the host controller. | 11-11-2010 |
20110022780 | RESTORE INDEX PAGE - Techniques for restoring index pages stored in non-volatile memory are disclosed where the index pages map logical sectors into physical pages. Additional data structures in volatile and non-volatile memory can be used by the techniques for restoring index pages. In some implementations, a lookup table associated with data blocks in non-volatile memory can be used to provide information regarding the mapping of logical sectors into physical pages. In some implementations, a lookup table associated with data blocks and a range of logical sectors and/or index pages can be used. | 01-27-2011 |
20110022781 | CONTROLLER FOR OPTIMIZING THROUGHPUT OF READ OPERATIONS - A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin. | 01-27-2011 |
20110022819 | INDEX CACHE TREE - Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the location of the first lookup table in non-volatile memory. An index cache tree in volatile memory holds the physical addresses of the most recently written or accessed logical sectors in a compressed format. | 01-27-2011 |
20110066789 | FILE SYSTEM DERIVED METADATA FOR MANAGEMENT OF NON-VOLATILE MEMORY - A file system programs metadata on a non-volatile memory device. The metadata can include data associating files with ranges of logical block addresses. During a garbage collection process, the data can be used to determine portions of physical blocks of the non-volatile memory device that are associated with files that have been deleted. Using the programmed metadata during garbage collection results in erasure of larger portions of blocks and improved wear leveling. | 03-17-2011 |
20110066869 | Memory Array Power Cycling - In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both. | 03-17-2011 |
20110154163 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 06-23-2011 |
20120072807 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 03-22-2012 |
20120216079 | Obtaining Debug Information from a Flash Memory Device - This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations. | 08-23-2012 |
20130007333 | Controller Interface Providing Improved Signal Integrity - In one implementation, a memory device includes non-volatile memory and a memory controller communicatively coupled to the non-volatile memory over a first bus. The memory device can also include a host device interface through which the memory controller communicates with a host device over a second bus, wherein the host device interface includes an impedance calibration circuit that is adapted to calibrate a signal transmitted over the second bus by host device interface so that a source impedance associated with the signal matches, within a threshold value, a load impedance associated with the host device over the second bus. | 01-03-2013 |
20130007347 | Booting a Memory Device from a Host - In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory accessible by a controller of the memory device; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, firmware from a host device, wherein the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the firmware from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained through communication with the memory controller of the memory device. | 01-03-2013 |
20130007348 | Booting Raw Memory from a Host - In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, one or more trim values from the host device, wherein the trim values define one or more parameters for accessing the non-volatile memory, and the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the trim values from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained by providing commands to the memory device. | 01-03-2013 |
20130007562 | Controller Interface Providing Improved Data Reliability - In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus. | 01-03-2013 |
20130036254 | DEBUGGING A MEMORY SUBSYSTEM - In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller. | 02-07-2013 |
20130036255 | TESTING MEMORY SUBSYSTEM CONNECTIVITY - In one implementation, a memory subsystem includes a plurality of non-volatile memory dies, a memory controller that is communicatively connected to each of the non-volatile memory dies over one or more first busses, a host interface through which the memory controller communicates with a host over a second bus, and a joint test action group (JTAG) interface through which the host performs a boundary scan of the memory subsystem including, at least, the non-volatile memory dies and the memory controller. The memory subsystem can be configured to be a subunit of a board-level memory device that includes the host. | 02-07-2013 |
20130073788 | WEAVE SEQUENCE COUNTER FOR NON-VOLATILE MEMORY SYSTEMS - Systems and methods are disclosed for providing a weave sequence counter (“WSC”) for non-volatile memory (“NVM”) systems. The WSC can identify the sequence in which each page of the NVM is programmed. The “weave” aspect can refer to the fact that multiple blocks can be open for programming at once, thus allowing the pages of these blocks to be programmed in a “woven” manner. Systems and methods are also disclosed for providing a host weave sequence counter (“HWSC”). Each time new data is initially programmed to the NVM, this data can be associated with a particular HWSC. The HWSC associated with the data may not change, even when the data is moved to a new page (e.g., for wear leveling purposes and the like). The WSC and HWSC may aid in, for example, performing rollback, building logical-to-physical mappings, determining static-versus-dynamic page statuses, and performing maintenance operations (e.g., wear leveling). | 03-21-2013 |
20130073789 | SYSTEMS AND METHODS FOR CONFIGURING NON-VOLATILE MEMORY - Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up. | 03-21-2013 |
20130073800 | Multipage Preparation Commands For Non-Volatile Memory Systems - Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation. | 03-21-2013 |
20130111298 | SYSTEMS AND METHODS FOR OBTAINING AND USING NONVOLATILE MEMORY HEALTH INFORMATION | 05-02-2013 |
20130132653 | DATA PARTITIONING SCHEME FOR NON-VOLATILE MEMORIES - Systems and methods are disclosed for partitioning data for storage in a non-volatile memory (“NVM”), such as flash memory. In some embodiments, a priority may be assigned to data being stored, and the data may be logically partitioned based on the priority. For example, a file system may identify a logical address within a first predetermined range for higher priority data and within a second predetermined range for lower priority data, such using a union file system. Using the logical address, a NVM driver can determine the priority of data being stored and can process (e.g., encode) the data based on the priority. The NVM driver can store an identifier in the NVM along with the data, and the identifier can indicate the processing techniques used on the associated data. | 05-23-2013 |
20130138868 | SYSTEMS AND METHODS FOR IMPROVED COMMUNICATIONS IN A NONVOLATILE MEMORY SYSTEM - Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels. | 05-30-2013 |
20130151754 | LBA BITMAP USAGE - Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance. | 06-13-2013 |
20130151830 | MOUNT-TIME RECONCILIATION OF DATA AVAILABILITY - Systems and methods are disclosed for mount-time reconciliation of data availability. During system boot-up, a non-volatile memory (“NVM”) driver can be enumerated, and an NVM driver mapping can be obtained. The NVM driver mapping can include the actual availability of LBAs in the NVM. A file system can then be mounted, and a file system allocation state can be generated. The file system allocation state can indicate the file system's view of the availability of LBAs. Subsequently, data availability reconciliation can be performed. That is, the file system allocation state and the NVM driver mapping can be overlaid and compared with one another in order to expose any discrepancies. | 06-13-2013 |
20130212318 | ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 08-15-2013 |
20130283081 | Memory Array Power Cycling - In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both. | 10-24-2013 |
20130290606 | POWER MANAGEMENT FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for power management of a system having non-volatile memory (“NVM”). One or more controllers of the system can optimally turn modules on or off and/or intelligently adjust the operating speeds of modules and interfaces of the system based on the type of incoming commands and the current conditions of the system. This can result in optimal system performance and reduced system power consumption. | 10-31-2013 |
20130326113 | USAGE OF A FLAG BIT TO SUPPRESS DATA TRANSFER IN A MASS STORAGE SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for usage of a flag bit to suppress data transfer in a mass storage system having non-volatile memory (“NVM”). In some embodiments, a host of the system can issue queue-able trim commands by dispatching non-data transfer write commands to the NVM. In some embodiments, the host can track the read behavior of a particular application over a period of time. As a result, the host can maintain heuristics of logical sectors that are most frequently read together. The host can then notify the NVM to pre-fetch data that the application will most likely request at some point in the future. These notifications can take the form of non-data transfer read commands. Each non-data transfer read commands can include a flag bit that is set to indicate that no data transfer is desired. | 12-05-2013 |
20140019673 | DYNAMICALLY ALLOCATING NUMBER OF BITS PER CELL FOR MEMORY LOCATIONS OF A NON-VOLATILE MEMORY - Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location. | 01-16-2014 |
20140136771 | Initiating Memory Wear Leveling - Systems and processes may use a host and an external host. The host may be a portable device that includes a memory, a memory controller, and a communication interface for communication with the external host. The portable device may receive a command signal from the external host and initiate a predetermined amount of wear leveling in response to the command signal. | 05-15-2014 |
20140164717 | Systems and Methods for Improved Communications in a Nonvolatile Memory System - Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels. | 06-12-2014 |
20140281136 | SYSTEMS AND METHODS FOR WRITING TO HIGH-CAPACITY MEMORY - Systems and methods for writing to high-capacity memory are disclosed. In high-capacity memory systems in which the capacity of the characteristic portion of the memory (e.g., a page of NAND flash memory) exceeds the capacity of a buffer used to write to the memory, underutilization issues are prevalent. Data organized in the buffer can be combined with additional data to improve utilization of the characteristic portion. According to various embodiments, the additional data can include duplicate copies of the data, whitened data, or any other suitable type of data. | 09-18-2014 |
20140281176 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 09-18-2014 |
20140281588 | GENERATING EFFICIENT READS FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred. | 09-18-2014 |
20140297935 | MOUNT-TIME RECONCILIATION OF DATA AVAILABILITY - Systems and methods are disclosed for mount-time reconciliation of data availability. During system boot-up, a non-volatile memory (“NVM”) driver can be enumerated, and an NVM driver mapping can be obtained. The NVM driver mapping can include the actual availability of LBAs in the NVM. A file system can then be mounted, and a file system allocation state can be generated. The file system allocation state can indicate the file system's view of the availability of LBAs. Subsequently, data availability reconciliation can be performed. That is, the file system allocation state and the NVM driver mapping can be overlaid and compared with one another in order to expose any discrepancies. | 10-02-2014 |