Patent application number | Description | Published |
20080207166 | Method and Apparatus for Providing a Data Protocol Voice Enabled Subscription Lock for a Wireless Communication Device - A method and system for restricting at least partial usage of a wireless communication device ( | 08-28-2008 |
20090134836 | DEVICES AND METHODS FOR ELECTRONIC DEVICE RECHARGING - Disclosed are devices and methods for regulating providing a charge via a charge receiving port of one device, the one device coupled to another device having a charge providing port. In one embodiment, the ports can be coupled by a cable. In another embodiment, the ports can be coupled wirelessly. The charge delivering device may regulate a charge providing process, controlled by a charge regulating controller of the charge providing device and based, for example, upon predetermined criteria. A charge regulating controller can disable the charging process, monitor the charge depletion rate, or the charging process may be based upon user established criteria. A charge regulating controller of the other device can regulate the charge accepting process. Each device may take on both roles, that is providing charge and receiving charge. | 05-28-2009 |
20100159955 | Method and Apparatus for Providing Location-Based Information - A method and apparatus for providing location-based information to a wireless communication device is disclosed. The wireless communication device receives its geographic position information and provides its geographic position information to a web server while accessing a web service provided by the web server. Based on the geographic position information received from the wireless communication device, the web server provides geographic coordinates of locations relevant to the web service in the form of web geo-cookies. The wireless communication device maintains a database of the received geographic coordinates. When the wireless communication accesses a geographic map of a route or region, the wireless communication device determines if the geographic coordinates in the database lie within boundaries of the accessed map. The geographic coordinates that lie within boundaries of the received map are annotated and displayed on the wireless communication device. | 06-24-2010 |
20130163733 | LOCATION AWARE SPEED DIAL ON A COMMUNICATION DEVICE - A method of assigning contacts to a speed dial function. The method can include identifying contacts that are candidates to be assigned to the speed dial function on a communication device. The method also can include identifying a geographic distance between each of the identified candidates and the communication device. The method further can include, via a processor, assigning a first of the identified candidates that is closest to the communication device to a first speed dial indicator, and assigning a second of the identified candidates that is next closest to the communication device to a second speed dial indicator. | 06-27-2013 |
20130265238 | Communication Device and Method for Visual Speed Dial - A communication device for visual speed dial is described. The communication device comprises a user interface, a display and a transmitter. The user interface detects activation of a speed dial mode. The display provides virtual keys in response to detecting activation of the speed dial mode. The virtual keys include characters associated with one or more phone numbers. One or more keys are associated with a particular phone number and a photographic image associated with the particular phone number. The user interface detects selection of the key or keys associated with the particular phone number and the photographic image. The transmitter communicates with a remote device in response to detecting selection of the key or keys. | 10-10-2013 |
20130281154 | MULTI-MODE METHODS AND DEVICES UTLIZING BATTERY POWER LEVEL FOR SELECTION OF THE MODES - Disclosed are a methods and devices in a battery-powered multimode wireless communication device ( | 10-24-2013 |
20140136643 | Dynamic Buffer Management for a Multimedia Content Delivery System - A method implemented in a computing device that connects over a network to server computers that host content streams. The method displays content items on the computing device, where each content item includes a link to one of the content streams, determines an amount of available bandwidth on a data connection from the computing device to the network, and associates a pre-fetch buffer and a streaming buffer with each content item. For each content item, the method obtains a measurement based on a condition relative to the linked content stream. The method then calculates, for each content item, a size for the pre-fetch buffer based on the amount of available bandwidth and the measurement, allocates memory for the pre-fetch buffer and the streaming buffer, and initiates a download of a first portion of the linked content stream to the pre-fetch buffer. | 05-15-2014 |
20140155041 | RADIO INTERFACE LAYER DESIGN FOR SMARTPHONES - A method and system communicates a request between a user application and a modem within a wireless communication device. A radio interface layer (RIL) architecture includes an application framework which receives a hardware specific request as a first application programming interface (API) call from the user application. In response to receiving the request, the application framework sends a corresponding, second API call to a vendor radio interface layer (Vendor RIL) which provides an interface configured for communicating with a specific type of transceiver or modem. In one embodiment, the second API call is transmitted via a Java Native interface (JNI). The JNI provides access to software programs associated with the transceiver, which programs are written in a language that is different from Java. The Vendor RIL communicates with the modem using a modem protocol software corresponding to the specific type of modem to perform commands associated with the request. | 06-05-2014 |
20140191041 | MOBILE DEVICES WITH RFID CAPABILITIES AND CORRESPONDING MEMORY WRITE METHODS - An electronic device ( | 07-10-2014 |
20140191846 | MOBILE DEVICE WITH RFID CAPABILITY AND CORRESPONDING BOOT SEQUENCE - An electronic device ( | 07-10-2014 |
20140273820 | AUTOMATIC USER NOTIFICATION, WITH QUICK RESPONSE (QR) CODE GENERATION FOLLOWING FAILED NFC DEVICE PAIRING - A first user equipment (UE) includes a display, at least two communication mechanisms that respectively supports a first and a second communication mode, and a processor communicatively coupled to the display and the communication mechanisms. The first UE further includes a failed pairing notification (FPN) utility that configures the first UE to: initiate communication with a second UE via a first communication mode; and in response to a trigger condition indicating that the first communication mode is not supported at either the first UE or the second UE, generate a notification alerting a user of the first UE that (1) a different communication mode is required for the first UE to communicate with the second UE and (2) an authorization QR code is required to be exchanged between the first UE and the second UE as an authentication mechanism before the communication can be established via the different communication mode. | 09-18-2014 |
20140273983 | Communication Device and Method for Enhanced Speed Dial - A communication device for enhanced speed dial is described. The communication device comprises a user interface, a display and a transmitter. The user interface detects activation of a speed dial mode. The display provides keys in response to detecting activation of the speed dial mode. The keys include characters associated with one or more phone numbers. One or more keys are associated with a particular phone number of a meeting notice of a scheduling application. The user interface detects selection of the key or keys associated with the particular phone number. The transmitter communicates with a remote device in response to detecting selection of the key or keys. | 09-18-2014 |
20140273984 | Communication Device and Method for Enhanced Speed Dial - A communication device for enhanced speed dial is described. The communication device comprises a user interface, a display and a transmitter. The user interface detects activation of a speed dial mode. The display provides keys in response to detecting activation of the speed dial mode. The keys include characters associated with one or more phone numbers. One or more keys are associated with a particular phone number of a recent call list of the communication device. The user interface detects selection of the key or keys associated with the particular phone number. The transmitter communicates with a remote device in response to detecting selection of the key or keys. | 09-18-2014 |
20140282923 | DEVICE SECURITY UTILIZING CONTINUALLY CHANGING QR CODES - A method provides device access security via use of periodically changing Quick Response (QR) codes. The method includes: generating a first authentication QR code and assigning the generated QR code as the current authentication mechanism for accessing the device. Contemporaneously with the generation of the QR code, at least one QR code validity parameter is established to define when access to the device can be provided to a second device that provides the correct authentication QR code along with the access request. The method includes, in response to a pre-defined trigger of the QR code validity parameter: generating a new authentication QR code, different from a previously generated authentication QR code; assigning the new authentication QR code as the current authentication mechanism for accessing the device; and enabling access to the first device to only second devices that provide the current authentication QR code as the authentication mechanism. | 09-18-2014 |
20140335916 | Method and Device for Determining User Handedness and Controlling a User Interface - A handheld portable device ( | 11-13-2014 |
20140348127 | MICRO TO MACRO IP CONNECTION HANDOVER - Disclosed are a system and method for moving a connection from a localized network, e.g., a personal area network (“PAN”), to a different or larger network, e.g., a wide area network (“WAN”). In one aspect, wherein two devices are in communication on a PAN, each device uses the PAN to query the IPv6 WAN prefix assigned to each other device to which it is communicating on the PAN. The querying device then creates a globally routable IPv6 address for the desired communication and uses it to continue the connection after the device detects that the PAN is out of range. In an embodiment, one of the endpoint devices may determine that it has changed its IPv6 prefix and may transmit the new prefix to the other device through an out-of-band method such as the Short Message Service. | 11-27-2014 |
20150087231 | DEVICE AUTO PAIRING WITHOUT TOUCH AND TAP - A device-to-device (D2D) pairing assembly comprises: a first and a second device detecting and communicating (DDC) component communicatively coupled to each other and to a microprocessor that executes a device pairing parameter exchange (DPPE) utility, which configures the D2D pairing assembly to: detect a communicative coupling of a first user device to the first DDC component; receive from the first user device at least one first pairing parameter, which first pairing parameter enables another device to connect to and participate in a pairing session with the first user device; detect a communicative coupling of a second user device to the second DDC component; and communicate the at least one first pairing parameter to the second user device, via the second DDC component, to trigger the second user device to connect to and participate in a pairing session with the first user device via a direct device-to-device communication channel. | 03-26-2015 |
20150244715 | DEVICE SECURITY UTILIZING CONTINUALLY CHANGING QR CODES - A method provides device access security via use of periodically changing Quick Response (QR) codes. The method includes: generating ( | 08-27-2015 |
20150371650 | Communicating Information Between Devices Using Ultra High Frequency Audio - A client device encodes data into an audio signal and communicates the audio data to an additional client device, which decodes the data from the audio signal. The data is partitioned into characters, which are subsequently partitioned into a plurality of sub-characters. Each sub-character is encoded into a frequency, and multiple frequencies that encode sub-characters are combined by the client device to generate an audio signal. Frequencies encoding sub-characters may be above 16 kilohertz, so the sub-characters are transmitted using frequencies that are inaudible to humans. The audio signal is communicated to an additional client device, which decodes frequencies from the audio signal to sub-characters, which are then combined into characters by the additional client device to generate the data. | 12-24-2015 |
20160037574 | DEVICE AUTO PAIRING WITHOUT TOUCH AND TAP - A device-to-device (D2D) pairing assembly comprises: a first and a second device detecting and communicating (DDC) component communicatively coupled to each other and to a microprocessor that executes a device pairing parameter exchange (DPPE) utility, which configures the D2D pairing assembly to: detect a communicative coupling of a first user device to the first DDC component; receive from the first user device at least one first pairing parameter, which first pairing parameter enables another device to connect to and participate in a pairing session with the first user device; detect a communicative coupling of a second user device to the second DDC component; and communicate the at least one first pairing parameter to the second user device, via the second DDC component, to trigger the second user device to connect to and participate in a pairing session with the first user device via a direct device-to-device communication channel. | 02-04-2016 |
Patent application number | Description | Published |
20120257509 | METHOD AND APPARATUS FOR COMMUNICATING DELIVER OF DATA PACKETS TO A USER EQUIPMENT IN A WIRELESS COMMUNICATION SYSTEM - In a communication system ( | 10-11-2012 |
20130072213 | Methods And Apparatus For Radio Resource Allocation - Systems and techniques for scheduling of use of resources by wireless devices and allocation of resources among devices. Information is received relating to channel efficiency experienced by a user equipment and also to the channel efficiency experienced by other user equipments. The information may include channel gain. Scheduling and resource allocation are performed so as to provide service to each device while minimizing interference penalties imposed by devices on one another. Scheduling and resource allocation may be evaluated and conducted through a number of mechanisms, such as ranking users according to transmit power, ranking user equipments according to target signal to noise ratios, and evaluation of relative advantages to users with the evaluation being performed resource block by resource block. The various metrics take into account both advantages to a particular user equipment under consideration and detrimental effects on other user equipment. | 03-21-2013 |
20140126481 | Block Scheduling Method For Scalable And Flexible Scheduling In A HSUPA System - A method for block scheduling of users is described. The method includes, in response to determining that a number of users in a wireless network exceed a threshold number, allotting the users into k block. The value of k is at least two. For each block, the method performs determining residual information for the block. The method also includes, for each block of the k blocks, loading into a fast-access memory user data for users in the block and scheduling the block in a scheduling period based at least in part on the user data and the residual information for k−1 other blocks. Apparatus and computer readable media are also described. | 05-08-2014 |
20150063222 | COORDINATED SCHEDULING WITH ADAPTIVE MUTING - Systems, methods, apparatuses, and computer program products relating to coordinated scheduling with adaptive muting are provided. One method comprises transmitting, by a network element, calculated impact information for a cell of the network element when taking an action related to a cell of the network element and/or taking an action related to a cell of a second network element. The method may also comprise transmitting a request for taking the action related to the cell of the second network element under certain circumstances | 03-05-2015 |
20150065108 | COORDINATED SCHEDULING WITH ADAPTIVE MUTING - Systems, methods, apparatuses, and computer program products relating to coordinated scheduling with adaptive muting are provided. One method comprises transmitting, by a network element, calculated impact information for a cell of the network element when taking an action related to a cell of the network element and/or taking an action related to a cell of a second network element. The method may also comprise transmitting a request for taking the action related to the cell of the second network element under certain circumstances | 03-05-2015 |
Patent application number | Description | Published |
20120079102 | Requester Based Transaction Status Reporting in a System with Multi-Level Memory - A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed. | 03-29-2012 |
20120079155 | Interleaved Memory Access from Multiple Requesters - A shared memory system having multiple banks is coupled to a set of requesters. Separate arbitration and control logic is provided for each bank, such that each bank can be accessed individually. The separate arbitration logics individually arbitrate transaction requests targeted to each bank of the memory. Access is granted to each bank on each access cycle to a highest priority request for each bank, such that more than one transaction request may be granted access to the memory on a same access cycle. A wide transaction request that has a transaction width that is wider than a width of one bank is divided into a plurality of divided requests. | 03-29-2012 |
20120198164 | Programmable Address-Based Write-Through Cache Control - This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write- back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit. | 08-02-2012 |
20120198165 | Mechanism to Update the Status of In-Flight Cache Coherence In a Multi-Level Cache Hierarchy - Separate buffers store snoop writes and direct memory access writes. A multiplexer selects one of these for input to a FIFO buffer. The FIFO buffer is split into multiple FIFOs including: a command FIFO; an address FIFO; and write data FIFO. Each snoop command is compared with an allocated line set and way and deleted on a match to avoid data corruption. Each snoop command is also compared with a victim address. If the snoop address matches victim address logic redirects the snoop command to a victim buffer and the snoop write is completed in the victim buffer. | 08-02-2012 |
20120198166 | Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache - The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register. | 08-02-2012 |
20120324174 | Multi-Port Register File with an Input Pipelined Architecture and Asynchronous Read Data Forwarding - In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file. | 12-20-2012 |
20120324175 | Multi-Port Register File with an Input Pipelined Architecture with Asynchronous Reads and Localized Feedback - In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored. | 12-20-2012 |
20130275822 | At Speed Testing of High Performance Memories with a Multi-Port BIS Engine - A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality of BIST memory ports are used to generate multiple memory test instructions in parallel, and the parallel instructions are then merged to generate a single memory test instruction stream at a speed that is a multiple of the BIST operating frequency. | 10-17-2013 |
20140108737 | ZERO CYCLE CLOCK INVALIDATE OPERATION - A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be trated as a cache miss to ensure that the requesting CPU will receive valid data. | 04-17-2014 |
20140122810 | PARALLEL PROCESSING OF MULTIPLE BLOCK COHERENCE OPERATIONS - A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream. | 05-01-2014 |
20140164844 | pBIST ENGINE WITH DISTRIBUTED DATA LOGGING - A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths. | 06-12-2014 |
20140164854 | pBIST ARCHITECTURE WITH MULTIPLE ASYNCHRONOUS SUB CHIPS OPERATING IN DIFFERRING VOLTAGE DOMAINS - A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains. | 06-12-2014 |
20140164855 | pBIST READ ONLY MEMORY IMAGE COMPRESSION - A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories. | 06-12-2014 |
20140164856 | pBIST ENGINE WITH REDUCED SRAM TESTING BUS WIDTH - A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST. | 06-12-2014 |
20150019840 | Highly Integrated Scalable, Flexible DSP Megamodule Architecture - This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error. | 01-15-2015 |
20160026569 | ZERO CYCLE CLOCK INVALIDATE OPERATION - A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be treated as a cache miss to ensure that the requesting CPU will receive valid data. | 01-28-2016 |
20160034396 | Programmable Address-Based Write-Through Cache Control - This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit. | 02-04-2016 |
Patent application number | Description | Published |
20130120419 | Memory Controller for Video Analytics and Encoding - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 05-16-2013 |
20130272620 | Analytics Assisted Encoding - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 10-17-2013 |
20130278775 | Multiple Stream Processing for Video Analytics and Encoding - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 10-24-2013 |
20130322551 | Memory Look Ahead Engine for Video Analytics - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 12-05-2013 |
20130322552 | Capturing Multiple Video Channels for Video Analytics and Encoding - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 12-05-2013 |
20130329137 | Video Encoding in Video Analytics - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 12-12-2013 |
20140040570 | On Die/Off Die Memory Management - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 02-06-2014 |
20140294102 | Intelligent MSI-X Interrupts for Video Analytics and Encoding - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 10-02-2014 |
20150189285 | Analytics Assisted Encoding - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 07-02-2015 |
Patent application number | Description | Published |
20090174458 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 07-09-2009 |
20110032020 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 02-10-2011 |
20110255351 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 10-20-2011 |
20120275236 | Method and Apparatus for Power Domain Isolation during Power Down - An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain. The signals may be conveyed to the circuitry in the first power domain via passgate circuits. When powering down the circuitry of the first and second power domains, a control circuit may first deactivate the passgate circuits in order to isolate the circuitry of the first power domain from that of the second power domain. The circuitry in the second power domain may be powered off subsequent to deactivating the passgate circuits. The circuitry in the first power domain may be powered off subsequent to powering off the circuitry in the second power domain. | 11-01-2012 |
20130154712 | Multiplexer with Level Shifter - A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter. | 06-20-2013 |
20140177354 | ZERO KEEPER CIRCUIT WITH FULL DESIGN-FOR-TEST COVERAGE - A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input. | 06-26-2014 |
Patent application number | Description | Published |
20140040518 | MEMORY INTERFACE - The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation. | 02-06-2014 |
20150248316 | SYSTEM AND METHOD FOR DYNAMICALLY SELECTING BETWEEN MEMORY ERROR DETECTION AND ERROR CORRECTION - Example methods, systems, and apparatus to dynamically select between memory error detection and memory error correction are disclosed herein. An example system includes a buffer, to store a flag settable to a first value to indicate that a memory page is to store error protection information to detect but not correct errors in the memory page. The flag is settable to a second value to indicate that the error protection information is to detect and correct errors for the memory page. The example system includes a memory controller to receive a request based on the flag to enable error detection without correction for the memory page when the flag is set to the first value, and to enable error detection and correction for the memory page when the flag is set to the second value. | 09-03-2015 |
20150364191 | NON-VOLATILE MULTI-LEVEL-CELL MEMORY WITH DECOUPLED BITS FOR HIGHER PERFORMANCE AND ENERGY EFFICIENCY - A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies. | 12-17-2015 |
20150373433 | RADIX ENHANCEMENT FOR PHOTONIC PACKET SWITCH - A system can include an optical multiplexer to combine a plurality of optical input signals having respective wavelengths into a wide-channel optical input signal that is provided to an input channel. The system also includes a photonic packet switch comprising a switch core and a plurality of ports defining a switch radix of the photonic packet switch. The input channel and an output channel can be associated with one of the plurality of ports. The photonic packet switch can process the wide-channel optical input signal and can generate a wide-channel optical output signal that is provided to the output channel. The system further includes an optical demultiplexer to separate the wide-channel optical output signal into a plurality of optical output signals having respective wavelengths. The optical multiplexer and the optical demultiplexer can collectively provide the system with a radix greater than the switch radix. | 12-24-2015 |
20160055095 | STORING DATA FROM CACHE LINES TO MAIN MEMORY BASED ON MEMORY ADDRESSES - A method for performing memory operations is provided. One or more processors can determine that at least a portion of data stored in a cache memory of the one or more processors is to be stored in the main memory. One or more ranges of addresses of the main memory is determined that correspond to a plurality of cache lines in the cache memory. A set of cache lines corresponding to addresses in the one or more ranges of addresses is identified, so that data stored in the identified set can be stored in the main memory. For each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, data stored in that cache line is caused to be stored in the main memory. | 02-25-2016 |
20160062821 | INVOKING AN ERROR HANDLER TO HANDLE AN UNCORRECTABLE ERROR - A detector detects, using an error code, an error in data stored in a memory. The detector determines whether the error is uncorrectable using the error code. In response to determining that the error is uncorrectable, an error handler associated with an application is invoked to handle the error in the data by recovering the data to an application-wide consistent state. | 03-03-2016 |
20160077922 | Advanced Versioned Memory - According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored. | 03-17-2016 |
20160078930 | REPRESENTING DATA USING A GROUP OF MULTILEVEL MEMORY CELLS - A memory device includes a group or block of k-level memory cells, where k>2, and where each of the k-level memory cells has k programmable states represented by respective resistance levels. | 03-17-2016 |
20160103766 | LOOKUP OF A DATA STRUCTURE CONTAINING A MAPPING BETWEEN A VIRTUAL ADDRESS SPACE AND A PHYSICAL ADDRESS SPACE - A memory region stores a data structure that contains a mapping between a virtual address space and a physical address space of a memory. A portion of the mapping is cached in a cache memory. In response to a miss in the cache memory responsive to a lookup of a virtual address of a request, an indication is sent to the buffer device. In response to the indication, a hardware controller on the buffer device performs a lookup of the data structure in the memory region to find a physical address corresponding to the virtual address. | 04-14-2016 |
Patent application number | Description | Published |
20110119525 | CHECKPOINTING IN MASSIVELY PARALLEL PROCESSING - One embodiment is a method that performs a local checkpoint at a processing node in a massively parallel processing (MPP) system that executes a workload with a plurality of processing nodes. The local checkpoint is stored in local memory of the processing node. While the workload continues to execute, a global checkpoint is performed from the local checkpoint stored in the local memory. | 05-19-2011 |
20110246828 | Memory Checkpointing Using A Co-Located Processor and Service Processor - A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime. | 10-06-2011 |
20120017065 | PARALLELIZED CHECK POINTING USING MATs AND THROUGH SILICON VIAs (TSVs) - A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs. | 01-19-2012 |
20120151159 | INTERFACE METHODS AND APPARATUS FOR MEMORY DEVICES - A disclosed example apparatus includes an interface ( | 06-14-2012 |
20120185727 | COMPUTING SYSTEM RELIABILITY - Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices. | 07-19-2012 |
20120233472 | SECURING NON-VOLATILE MEMORY REGIONS - Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region. | 09-13-2012 |
20120268983 | RANDOM-ACCESS MEMORY WITH DYNAMICALLY ADJUSTABLE ENDURANCE AND RETENTION - A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality. | 10-25-2012 |
20120272036 | ADAPTIVE MEMORY SYSTEM - An adaptive, memory system is provided. The adaptive memory system has a number of physical-memory devices and a memory controller that creates and maintains a logical address space to which the physical-memory devices and data-storage allocations are mapped, and through which mapping the memory controller matches static, dynamic, and dynamically-adjustable retention and resiliency characteristics of portions of the physical-memory devices with specified retention and resiliency characteristics specified for the data-storage allocations. | 10-25-2012 |
20120272039 | RETENTION-VALUE ASSOCITED MEMORY - A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address. | 10-25-2012 |
20120278650 | CONTROLLING NANOSTORE OPERATION BASED ON MONITORED PERFORMANCE - Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore. | 11-01-2012 |
20120278651 | Remapping data with pointer - Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block. | 11-01-2012 |
20120324156 | METHOD AND SYSTEM OF ORGANIZING A HETEROGENEOUS MEMORY ARCHITECTURE - An exemplary embodiment of the present invention may build data blocks in non-volatile memory. The corresponding parity blocks may be built in a fast, high endurance memory. | 12-20-2012 |
20130111147 | METHODS AND APPARATUS TO ACCESS MEMORY | 05-02-2013 |
20130111295 | METHODS AND APPARATUS TO PERFORM ERROR DETECTION AND CORRECTION | 05-02-2013 |
20130117521 | Managing Chip Multi-Processors Through Virtual Domains - A chip multi-processor (CMP) with virtual domain management. The CMP has a plurality of tiles each including a core and a cache, a mapping storage, a plurality of memory controllers, a communication bus interconnecting the tiles and the memory controllers, and machine-executable instructions. The tiles and memory controllers are responsive to the instructions to group the tiles into a plurality of virtual domains, each virtual domain associated with at least one memory controller, and to store a mapping unique to each virtual domain in the mapping storage. | 05-09-2013 |
20130326293 | MEMORY ERROR TEST ROUTINE - An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure is to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored. | 12-05-2013 |
20140068209 | ACCESSING REMOTE MEMORY ON A MEMORY BLADE - A method of accessing remote memory comprising receiving a request for access to a page from a computing device, adding an address of the accessed page to a recent list memory on the remote memory, associating a recent list group identifier to a number of addresses of accessed pages, transferring the requested page to the computing device with the recent list group identifier and temporarily maintaining a copy of the transferred page on the remote memory. | 03-06-2014 |
20140157054 | MEMORY ERROR IDENTIFICATION BASED ON CORRUPTED SYMBOL PATTERNS - A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern. | 06-05-2014 |
20140173170 | MULTIPLE SUBARRAY MEMORY ACCESS - A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width (“MFW”) instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests. | 06-19-2014 |
20140208156 | MEMORY ACCESS METHODS AND APPARATUS - A disclosed example apparatus includes a row address register ( | 07-24-2014 |
20140247673 | ROW SHIFTING SHIFTABLE MEMORY - A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row. | 09-04-2014 |
20140351495 | LOCAL CHECKPOINTING USING A MULTI-LEVEL CELL - Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint. | 11-27-2014 |
20150074456 | VERSIONED MEMORIES USING A MULTI-LEVEL CELL - Versioned memories using a multi-level cell (MLC) are disclosed. An example method includes comparing a global memory version to a block memory version, the global memory version corresponding to a plurality of memory blocks, the block memory version corresponding to one of the plurality of memory blocks. The example method includes determining, based on the comparison, which level in a multi-level cell of the one of the plurality of memory blocks stores checkpoint data. | 03-12-2015 |
20150082122 | LOCAL ERROR DETECTION AND GLOBAL ERROR CORRECTION - A system may use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED may be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC, in response to identifying the error. | 03-19-2015 |
20150162078 | Multi-Level Cell Memory - A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from and write to the memory device, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer. | 06-11-2015 |
20150302904 | ACCESSING MEMORY - A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers. | 10-22-2015 |
Patent application number | Description | Published |
20130275782 | CONTROLLING POWER GATE CIRCUITRY BASED ON DYNAMIC CAPACITANCE OF A CIRCUIT - In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed. | 10-17-2013 |
20140181388 | Method And Apparatus To Implement Lazy Flush In A Virtually Tagged Cache Memory - A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed. | 06-26-2014 |
20140189659 | HANDLING OF BINARY TRANSLATED SELF MODIFYING CODE AND CROSS MODIFYING CODE - A processor core includes a processor to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed. | 07-03-2014 |
20150277911 | Instruction and Logic for a Logical Move in an Out-Of-Order Processor - A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register. | 10-01-2015 |
20150277914 | LOCK ELISION WITH BINARY TRANSLATION BASED PROCESSORS - Generally, this disclosure provides systems, devices, methods and computer readable media for detection and exploitation of lock elision opportunities with binary translation based processors. The device may include a dynamic binary translation (DBT) module to translate a region of code from a first instruction set architecture (ISA) to translated code in a second ISA and to detect and elide a lock associated with a critical section of the region of code. The device may also include a processor to speculatively execute the translated code in the critical section. The device may further include a transactional support processor to detect a memory access conflict associated with the lock and/or critical section during the speculative execution, roll back the speculative execution in response to the detection, and commit the speculative execution in the absence of the detection. | 10-01-2015 |
20150277916 | METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCESSOR PIPELINE - A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations. | 10-01-2015 |
20150277975 | Instruction and Logic for a Memory Ordering Buffer - A processor includes an allocator with logic assigning alias hardware resources to instructions within an atomic region of instructions. The atomic region includes reordered instructions. The processor also includes a dispatcher with logic to dispatch instructions from the atomic region of instructions for execution. Furthermore, the processor includes a memory execution unit with logic to populate the memory execution unit with the instructions from the atomic region of instructions including reordered instructions, receive snoop requests and determine whether the snoop request matches memory address data of elements within the memory execution unit, and prevent reassignment of alias hardware resources for any load instructions that are eligible to match the snoop requests. | 10-01-2015 |
20150378731 | APPARATUS AND METHOD FOR EFFICIENTLY IMPLEMENTING A PROCESSOR PIPELINE - Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor. | 12-31-2015 |
20160092222 | INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION - A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register. | 03-31-2016 |
Patent application number | Description | Published |
20120035941 | QUANTIZATION AND INVERSE QUANTIZATION FOR AUDIO - An audio encoder and decoder use architectures and techniques that improve the efficiency of quantization (e.g., weighting) and inverse quantization (e.g., inverse weighting) in audio coding and decoding. The described strategies include various techniques and tools, which can be used in combination or independently. For example, an audio encoder quantizes audio data in multiple channels, applying multiple channel-specific quantizer step modifiers, which give the encoder more control over balancing reconstruction quality between channels. The encoder also applies multiple quantization matrices and varies the resolution of the quantization matrices, which allows the encoder to use more resolution if overall quality is good and use less resolution if overall quality is poor. Finally, the encoder compresses one or more quantization matrices using temporal prediction to reduce the bitrate associated with the quantization matrices. An audio decoder performs corresponding inverse processing and decoding. | 02-09-2012 |
20120082316 | MULTI-CHANNEL AUDIO ENCODING AND DECODING - An audio encoder and decoder use architectures and techniques that improve the efficiency of multi-channel audio coding and decoding. The described strategies include various techniques and tools, which can be used in combination or independently. For example, an audio encoder performs a pre-processing multi-channel transform on multi-channel audio data, varying the transform so as to control quality. The encoder groups multiple windows from different channels into one or more tiles and outputs tile configuration information, which allows the encoder to isolate transients that appear in a particular channel with small windows, but use large windows in other channels. Using a variety of techniques, the encoder performs flexible multi-channel transforms that effectively take advantage of inter-channel correlation. An audio decoder performs corresponding processing and decoding. In addition, the decoder performs a post-processing multi-channel transform for any of multiple different purposes. | 04-05-2012 |
20120087504 | MULTI-CHANNEL AUDIO ENCODING AND DECODING - An audio encoder and decoder use architectures and techniques that improve the efficiency of multi-channel audio coding and decoding. The described strategies include various techniques and tools, which can be used in combination or independently. For example, an audio encoder performs a pre-processing multi-channel transform on multi-channel audio data, varying the transform so as to control quality. The encoder groups multiple windows from different channels into one or more tiles and outputs tile configuration information, which allows the encoder to isolate transients that appear in a particular channel with small windows, but use large windows in other channels. Using a variety of techniques, the encoder performs flexible multi-channel transforms that effectively take advantage of inter-channel correlation. An audio decoder performs corresponding processing and decoding. In addition, the decoder performs a post-processing multi-channel transform for any of multiple different purposes. | 04-12-2012 |
20120130721 | DIGITAL MEDIA UNIVERSAL ELEMENTARY STREAM - Described techniques and tools include techniques and tools for mapping digital media data (e.g., audio, video, still images, and/or text, among others) in a given format to a transport or file container format useful for encoding the data on optical disks such as digital video disks (DVDs). A digital media universal elementary stream can be used to map digital media streams (e.g., an audio stream, video stream or an image) into any arbitrary transport or file container, including optical disk formats, and other transports, such as broadcast streams, wireless transmissions, etc. The information to decode any given frame of the digital media in the stream can be carried in each coded frame. A digital media universal elementary stream includes stream components called chunks. An implementation of a digital media universal elementary stream arranges data for a media stream in frames, the frames having one or more chunks. | 05-24-2012 |
20120213286 | LOCAL PICTURE IDENTIFIER AND COMPUTATION OF CO-LOCATED INFORMATION - Video decoding innovations for using local picture identifiers and computing co-located information are described. In one aspect, a decoder identifies reference pictures in a reference picture list of a temporal direct prediction mode macroblock that match reference pictures used by a co-located macroblock using local picture identifiers. In another aspect, a decoder determines whether reference pictures used by blocks are the same by comparing local picture identifiers during calculation of boundary strength. In yet another aspect, a decoder determines a picture type of a picture and based on the picture type selectively skips or simplifies computation of co-located information for use in reconstructing direct prediction mode macroblocks outside the picture. | 08-23-2012 |
20130033612 | REDUCED LATENCY VIDEO STABILIZATION - Reduced latency video stabilization methods and tools generate truncated filters for use in the temporal smoothing of global motion transforms representing jittery motion in captured video. The truncated filters comprise future and past tap counts that can be different from each other and are typically less than those of a baseline filter providing a baseline of video stabilization quality. The truncated filter future tap count can be determined experimentally by comparing a smoothed global motion transform set generated by applying a baseline filter to a video segment to those generated by multiple test filter with varying future tap counts, then settings the truncated filter future tap count based on an inflection point on an error-future tap count curve. A similar approach can be used to determine the truncated filter past tap count. | 02-07-2013 |
20130108248 | IMPLEMENTING CHANNEL START AND FILE SEEK FOR DECODER | 05-02-2013 |
20130141642 | ADAPTIVE CONTROL OF DISPLAY REFRESH RATE BASED ON VIDEO FRAME RATE AND POWER EFFICIENCY - A battery operated device, having a display with two or more available refresh rates, has its refresh rate selected so as to match the video frame rate of video data played back on the display. This selection is made by coordinating the resources in the device that are used to process the video from its reception through to its display. | 06-06-2013 |
20130144630 | MULTI-CHANNEL AUDIO ENCODING AND DECODING - An audio encoder and decoder use architectures and techniques that improve the efficiency of multi-channel audio coding and decoding. The described strategies include various techniques and tools, which can be used in combination or independently. For example, an audio encoder performs a pre-processing multi-channel transform on multi-channel audio data, varying the transform so as to control quality. The encoder groups multiple windows from different channels into one or more tiles and outputs tile configuration information, which allows the encoder to isolate transients that appear in a particular channel with small windows, but use large windows in other channels. Using a variety of techniques, the encoder performs flexible multi-channel transforms that effectively take advantage of inter-channel correlation. An audio decoder performs corresponding processing and decoding. In addition, the decoder performs a post-processing multi-channel transform for any of multiple different purposes. | 06-06-2013 |
20130208901 | QUANTIZATION MATRICES FOR DIGITAL AUDIO - Quantization matrices facilitate digital audio encoding and decoding. An audio encoder generates and compresses quantization matrices; an audio decoder decompresses and applies the quantization matrices. The invention includes several techniques and tools, which can be used in combination or separately. For example, the audio encoder can generate quantization matrices from critical band patterns for blocks of audio data. The encoder can compute the quantization matrices directly from the critical band patterns, which can be computed from the same audio data that is being compressed. The audio encoder/decoder can use different modes for generating/applying quantization matrices depending on the coding channel mode of multi-channel audio data. The audio encoder/decoder can use different compression/decompression modes for the quantization matrices, including a parametric compression/decompression mode. | 08-15-2013 |
20130215978 | METADATA ASSISTED VIDEO DECODING - A video decoder is disclosed that uses metadata in order to make optimization decisions. In one embodiment, metadata is used to choose which of multiple available decoder engines should receive a video sequence. In another embodiment, the optimization decisions can be based on length and location metadata information associated with a video sequence. Using such metadata information, a decoder engine can skip start-code scanning to make the decoding process more efficient. Also based on the choice of decoder engine, it can decide whether emulation prevention byte removal shall happen together with start code scanning or not. | 08-22-2013 |
20140039884 | QUALITY IMPROVEMENT TECHNIQUES IN AN AUDIO ENCODER - An audio encoder implements multi-channel coding decision, band truncation, multi-channel rematrixing, and header reduction techniques to improve quality and coding efficiency. In the multi-channel coding decision technique, the audio encoder dynamically selects between joint and independent coding of a multi-channel audio signal via an open-loop decision based upon (a) energy separation between the coding channels, and (b) the disparity between excitation patterns of the separate input channels. In the band truncation technique, the audio encoder performs open-loop band truncation at a cut-off frequency based on a target perceptual quality measure. In multi-channel rematrixing technique, the audio encoder suppresses certain coefficients of a difference channel by scaling according to a scale factor, which is based on current average levels of perceptual quality, current rate control buffer fullness, coding mode, and the amount of channel separation in the source. In the header reduction technique, the audio encoder selectively modifies the quantization step size of zeroed quantization bands so as to encode in fewer frame header bits. | 02-06-2014 |
20140294094 | CUSTOM DATA INDICATING NOMINAL RANGE OF SAMPLES OF MEDIA CONTENT - A media processing tool adds custom data to an elementary media bitstream or media container. The custom data indicates nominal range of samples of media content, but the meaning of the custom data is not defined in the codec format or media container format. For example, the custom data indicates the nominal range is full range or limited range. For playback, a media processing tool parses the custom data and determines an indication of media content type. A rendering engine performs color conversion operations whose logic changes based at least in part on the media content type. In this way, a codec format or media container format can in effect be extended to support full nominal range media content as well as limited nominal range media content, and hence preserve full or correct color fidelity, while maintaining backward compatibility and conformance with the codec format or media container format. | 10-02-2014 |
20140316788 | QUALITY IMPROVEMENT TECHNIQUES IN AN AUDIO ENCODER - An audio encoder implements multi-channel coding decision, band truncation, multi-channel rematrixing, and header reduction techniques to improve quality and coding efficiency. In the multi-channel coding decision technique, the audio encoder dynamically selects between joint and independent coding of a multi-channel audio signal via an open-loop decision based upon (a) energy separation between the coding channels, and (b) the disparity between excitation patterns of the separate input channels. In the band truncation technique, the audio encoder performs open-loop band truncation at a cut-off frequency based on a target perceptual quality measure. In multi-channel rematrixing technique, the audio encoder suppresses certain coefficients of a difference channel by scaling according to a scale factor, which is based on current average levels of perceptual quality, current rate control buffer fullness, coding mode, and the amount of channel separation in the source. In the header reduction technique, the audio encoder selectively modifies the quantization step size of zeroed quantization bands so as to encode in fewer frame header bits. | 10-23-2014 |
20150036010 | GENERIC PLATFORM VIDEO IMAGE STABILIZATION - Video image stabilization provides better performance on a generic platform for computing devices by evaluating available multimedia digital signal processing components, and selecting the available components to utilize according to a hierarchy structure for video stabilization performance for processing parts of the video stabilization. The video stabilization has improved motion vector estimation that employs refinement motion vector searching according to a pyramid block structure relationship starting from a downsampled resolution version of the video frames. The video stabilization also improves global motion transform estimation by performing a random sample consensus approach for processing the local motion vectors, and selection criteria for motion vector reliability. The video stabilization achieves the removal of hand shakiness smoothly by real-time one-pass or off-line two-pass temporal smoothing with error detection and correction. | 02-05-2015 |
20160112630 | CAMERA CAPTURE RECOMMENDATION FOR APPLICATIONS - One or more techniques and/or systems are provided for camera capture recommendation. For example, an application may operate to capture an image using a capture device (e.g., a user may use a camera of a smart phone to capture a vacation photo for sharing through a social network app). Camera parameters of the capture device and/or a preview data stream (e.g., pixel data depicting a beach “seen” by the camera in real-time) may be used to generate a camera capture recommendation (e.g., a recommendation to use a haze removal module, a high dynamic range module, a focus bracketing module, etc.). The camera capture recommendation is provided to the application. In this way, the application may selectively use, override, supplement (e.g., use an application supplied module), or modify the camera capture recommendation for application to the capture device to obtain an output image. | 04-21-2016 |
20160112638 | VIDEO STABILIZATION USING PADDED MARGIN PIXELS - One or more techniques and/or systems are provided for video stabilization and/or for image frame generation. For example, a user may instruct a video application hosted on a smart phone to capture a video at a target resolution of 1080 pixels. A padded input having a padded resolution that is larger than the target resolution may be obtained from a capture device, such as a camera of the smart phone. The padded input may be provided to a video stabilization component to obtain a target image frame having the target resolution. In this way, the video stabilization component may perform cropping using padded margin pixels (e.g., additional pixels of the padded input beyond the 1080 pixels of the target resolution) so that image upscaling after cropping (e.g., to account for global warping, etc.) may be mitigated to reduce blur that may otherwise result from image upscaling. | 04-21-2016 |
Patent application number | Description | Published |
20110095359 | Field Boosted Metal-Oxide-Semiconductor Field Effect Transistor - A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions. | 04-28-2011 |
20130320462 | ADAPTIVE CHARGE BALANCED EDGE TERMINATION - In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings. | 12-05-2013 |
20140183624 | Adaptive Charge Balanced MOSFET Techniques - An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure includes a gate region surrounded by a gate insulator region. The field plate stack includes a plurality of field plate insulator regions, a plurality of field plate regions, and a field ring region. The plurality of field plates are separated from each other by respective field plate insulators. The body region is disposed between the gate structure, the source region, the drift region and the field ring region. Each of two or more field plates are coupled to the field ring. | 07-03-2014 |
20150372077 | PROCESSES USED IN FABRICATING A METAL-INSULATOR-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET. | 12-24-2015 |
Patent application number | Description | Published |
20130062614 | GROUP III-V ENHANCEMENT MODE TRANSISTOR WITH THYRISTOR GATE - An apparatus includes an enhancement mode transistor having multiple Group III-V layers above a substrate and a gate above the Group III-V layers. The gate includes multiple layers of material that form at least a portion of a thyristor. The multiple layers of material may include a first p-type layer of material, an n-type layer of material on the first p-type layer, and a second p-type layer of material on the n-type layer. The multiple layers of material may also include a p-type layer of material, an n-type layer of material on the p-type layer, and a Schottky metal layer on the n-type layer. The enhancement mode transistor may represent a high electron mobility transistor (HEMT) or a heterostructure field effect transistor (HFET). | 03-14-2013 |
20140042452 | III-NITRIDE ENHANCEMENT MODE TRANSISTORS WITH TUNABLE AND HIGH GATE-SOURCE VOLTAGE RATING - A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device. | 02-13-2014 |
20140327010 | AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS - A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value. | 11-06-2014 |
20140327011 | III-NITRIDE TRANSISTOR LAYOUT - A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate. | 11-06-2014 |
20140329370 | LAYER TRANSFER OF SILICON ONTO III-NITRIDE MATERIAL FOR HETEROGENOUS INTEGRATION - An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device. | 11-06-2014 |
20140339671 | METHOD TO FORM STEPPED DIELECTRIC FOR FIELD PLATE FORMATION - A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate. | 11-20-2014 |
20140374766 | BI-DIRECTIONAL GALLIUM NITRIDE SWITCH WITH SELF-MANAGED SUBSTRATE BIAS - A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp. | 12-25-2014 |
20150221747 | AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS - A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value. | 08-06-2015 |
20150243742 | METHOD TO FORM STEPPED DIELECTRIC FOR FIELD PLATE FORMATION - A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate. | 08-27-2015 |
20150270357 | III-NITRIDE DEVICE AND METHOD HAVING A GATE ISOLATING STRUCTURE - A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate. | 09-24-2015 |