Patent application number | Description | Published |
20120235276 | ELECTRODE TREATMENTS FOR ENHANCED DRAM PERFORMANCE - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 09-20-2012 |
20130069202 | Electrode Treatments for Enhanced DRAM Performance - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 03-21-2013 |
20130071991 | Electrode Treatments for Enhanced DRAM Performance - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 03-21-2013 |
20130143379 | LEAKAGE REDUCTION IN DRAM MIM CAPACITORS - A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly or non-doped material will become crystalline (≧30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack. | 06-06-2013 |
20150228710 | Methods to Improve Electrical Performance of ZrO2 Based High-K Dielectric Materials for DRAM Applications - A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (≧30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack. | 08-13-2015 |
Patent application number | Description | Published |
20140091677 | PIEZOELECTRIC ELEMENT - A piezoelectric element includes a substrate, a lower electrode layer, a piezoelectric layer, and an upper electrode layer. The lower electrode layer is fixed to the substrate and the piezoelectric layer is formed on the lower electrode layer. The upper electrode layer is formed on piezoelectric layer. The lower electrode layer contains pores therein and has a larger thermal expansion coefficient than the piezoelectric layer. | 04-03-2014 |
20150028444 | INFRARED DETECTION ELEMENT - An infrared detection element includes a substrate, a lower electrode layer, a pyroelectric layer, and an upper electrode layer. The lower electrode layer is fixed to the substrate, and the pyroelectric layer is formed on the lower electrode layer. The upper electrode layer is formed on pyroelectric layer. The lower electrode layer contains pores therein and has a larger thermal expansion coefficient than the pyroelectric layer. | 01-29-2015 |
20160035961 | DIELECTRIC ELEMENT AND PIEZOELECTRIC ELEMENT - A dielectric element includes a substrate, a first electrode layer on this substrate, a dielectric layer on the first electrode layer, and a second electrode layer on the dielectric layer. The first electrode layer contains lanthanum nickelate. The dielectric layer contains lead magnesate niobate-titanate represented by (1−x)Pb(Mg | 02-04-2016 |
Patent application number | Description | Published |
20080268639 | Method of Manufacturing A Semiconductor Integrated Circuit Device - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 10-30-2008 |
20090275193 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 11-05-2009 |
20110021022 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 01-27-2011 |
20110250752 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 10-13-2011 |
Patent application number | Description | Published |
20120014078 | Electronic Component Structure and Electronic Device - According to one embodiment, an electronic component structure includes an electronic component, an electrode, and a restriction portion. The electrode is connected to the electronic component in a multilayer state and comprises a plurality of solder regions on a side opposite to a side of the electronic component. Each of the solder regions is soldered to a substrate by separate solders. The restriction portion is connected to a periphery of the solder regions, and has a level difference relative to the solder regions. | 01-19-2012 |
20120250274 | Wiring Substrate and Electronic Device - In one embodiment, there is provided a wiring substrate. The wiring substrate includes: a substrate body comprising a first surface and a second surface opposite to the first surface, wherein the substrate body has a plurality of first through holes; a plurality of first pads on the first surface of the substrate body; a plurality of second pads on the first surface of the substrate body, wherein the second pads are surrounded by the first pads. Each of the second pads has at least one second through hole, and the second pads are disposed on the first surface of the substrate body such that each of the second through holes is communicated with a corresponding one of the first through holes. | 10-04-2012 |
20130141884 | Electronic Component Structure and Electronic Device - According to one embodiment, an electronic component structure includes an electronic component, an electrode, and a restriction portion. The electrode is connected to the electronic component in a multilayer state and comprises a plurality of solder regions on a side opposite to a side of the electronic component. Each of the solder regions is soldered to a substrate by separate solders. The restriction portion is connected to a periphery of the solder regions, and has a level difference relative to the solder regions. | 06-06-2013 |