Patent application number | Description | Published |
20090021312 | PLL circuit - It has been difficult that conventional PLL circuits have a suppression characteristic of suppressing the phase noise which is free of variation due to temperature and individual difference and stable in a wide frequency band. The present invention provides a PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved. | 01-22-2009 |
20090039973 | VCO driving circuit and frequency synthesizer - A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF | 02-12-2009 |
20090072947 | Control method for high-frequency radio equipment and high-frequency radio system - A control method for a high-frequency radio equipment and a high-frequency radio equipment system in spread spectrum radio data communication are provided which are interference-tolerant and can maintain transmission quality with improved receiving sensitivity. | 03-19-2009 |
20090134946 | Oscillation frequency control circuit - Provided is an oscillation frequency control circuit, which corrects its own frequency so that it can hold an oscillation frequency stably even when it does not have an input of a highly stable reference signal but makes a self-run. The oscillation frequency control circuit comprises a voltage-controlled oscillator, a frequency divider, a phase comparator, a loop filter, a detecting circuit for detecting an external reference signal, a PWM circuit for generating pulses, when pulse generating information inputs, to output the pulses to the loop filter, a memory for storing the pulse generating information corresponding to voltage information, a switch for turning ON/OFF the connection between the phase comparator and the loop filter, and a CPU for turning ON the switch, if the level of the external reference signal detected by the detecting circuit is within a proper range, but OFF the switch, if the level is outside of the proper range, thereby to output the pulse generating information stored in the memory, to the PWM circuit. | 05-28-2009 |
20100264961 | Oscillation frequency control circuit - Provided is an oscillation frequency control circuit for correcting its frequency, keeping the oscillation frequency stable when self-oscillating, and oscillating with a control voltage generated by making a fixed voltage given from outside variable. In the oscillation frequency control circuit, a CPU selects/outputs the control voltage preferentially according to a command of a control voltage selection. If the command is not given and the level of an outside reference signal detected by a detecting circuit is within an adequate range, it turns a select switch on. If the command is not given and the level of the outside reference signal is out of the adequate range, it turns the select switch off and outputs information about pulse generation stored in a memory to a PWM circuit. | 10-21-2010 |
20100264962 | VCO DRIVING CIRCUIT AND FREQUENCY SYNTHESIZER - A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF | 10-21-2010 |
20110032005 | Frequency synthesizer - A frequency synthesizer in which a satisfactory frequency stability can be obtained over the entire long period of service immediately after power activation is disclosed. The reference signal generation circuit includes an OCXO, a TCXO, weight converters which regulate weights with respect to outputs, and an adder which adds up the outputs from the weight converters to output the added output as a reference signal. The CPU controls weight converters B and C so that the weight of the TCXO is set to 100% and the weight of the OCXO is set to 0% at the time of the power activation, so that the weight of the OCXO gradually rises, and so that the weight of the TCXO is set to 0% and the weight of the OCXO is set to 100% after preset time, whereby the frequency can quickly be stabilized after the power activation. | 02-10-2011 |
20110204935 | PLL circuit - Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC. | 08-25-2011 |