Patent application number | Description | Published |
20120042176 | Method and Apparatus for Optimizing Clock Speed and Power Dissipation in Multicore Architectures - A multicore processor provides for local power control at each of the cores which is used to lower the maximum operating frequency of cores by any amount above of the maximum operating frequency of the slowest core. This power savings is then used to increase the maximum operating frequency of the frequency balanced cores within a power constraint. | 02-16-2012 |
20140047199 | Memory-Link Compression for Graphic Processor Unit - A graphic processing unit having multiple computational elements flexibly interconnected to memory elements provides for data compressors/decompressors in the memory channels communicating between the computational elements and memory elements to provide an effective increase in bandwidth of those connections by the compression of data transferred thereon. | 02-13-2014 |
20140068304 | METHOD AND APPARATUS FOR POWER REDUCTION DURING LANE DIVERGENCE - A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence. | 03-06-2014 |
20140280430 | Multiplier Circuit with Dynamic Energy Consumption Adjustment - A fixed point multiplier that can be used in mobile computer systems operating under limited power constraints provides a trade-off between computational accuracy and energy consumption that may be changed dynamically for energy conservation purposes. In one embodiment, the multiplier pre-stores multiplication shift coefficients to eliminate leading-one circuitry normally used in shift and accumulate multipliers. | 09-18-2014 |
20140325248 | APPARATUS AND METHOD FOR ADJUSTING BANDWIDTH - A method for adjusting bandwidth, a bandwidth scaler and an apparatus are provided. The method for adjusting bandwidth involves determining a dynamic context of a processor, and based on the determined dynamic context, scaling bandwidth between the processor and a memory. | 10-30-2014 |
20140337853 | Resource And Core Scaling For Improving Performance Of Power-Constrained Multi-Core Processors - A multi-core processor provides circuitry for jointly scaling the number of operating cores and the amount of resources per core in order to maximize processing performance in a power-constrained environment. Such scaling is advantageously provided without the need for scaling voltage and frequency. Selection of the number of operating cores and the amount of resources per core is made by examining the degree of instruction and thread level parallelism available for a given application. Accordingly, performance counters (and other characteristics) implemented in by a processor may be sampled on-line (in real time) and/or performance counters for a given application may be profiled and characterized off-line. As a result, improved processing performance may be achieved despite decreases in core operating voltages and increases in technology process variability over time. | 11-13-2014 |
20150113304 | ENERGY-EFFICIENT MULTICORE PROCESSOR ARCHITECTURE FOR PARALLEL PROCESSING - A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption. | 04-23-2015 |
20150128007 | Dynamic Error Handling For On-Chip Memory Structures - A memory structure is provided that controls the activation of error handling bits as a function of operating voltage. In this way, error correction can be used to offset errors when the memory structure is run at low voltage (and frequency). However, negative performance impacts for such error correction, such as additional access latencies, can be avoided when the memory structure is run at higher voltage (and frequency) and memory errors are less likely. In addition, increased latencies due to evaluating error handling bits may be hidden by reading digital data bits from the memory structures speculatively and assuming no errors. Also, certain portions of memory structures may have larger cells, and therefore larger areas, than other portions, which may provide not only higher reliability at low operating voltages, but also faster operation with reduced latency. | 05-07-2015 |