Nale
Bill Nale, Livermore, CA US
Patent application number | Description | Published |
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20120159059 | MEMORY INTERFACE SIGNAL REDUCTION - In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed. | 06-21-2012 |
20140040550 | MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS - A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol. | 02-06-2014 |
Bill Harry Nale, Livermore, CA US
Patent application number | Description | Published |
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20140112339 | HIGH PERFORMANCE INTERCONNECT - A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state | 04-24-2014 |
Kumar Nale, Lafayette, IN US
Patent application number | Description | Published |
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20140060039 | Turbocharger Having Compressor Cooling Arrangement and Method - A compressor adapted to compress a working fluid includes a housing surrounding a compressor wheel and a backplate connected to the housing and enclosing the compressor wheel within an interior space of the housing. A cooling fluid conduit is fluidly connected between a cooled and compressed source of working fluid downstream of the compressor and the interior space of the housing of the compressor at a location between the compressor wheel and the back plate. A pressure differential created when the compressor is operating draws a flow of cooled, compressed charge into the interior space of the housing, which flow passes over and convectively cools said compressor wheel before mixing with a main compressor flow and being provided back through the compressor outlet. | 03-06-2014 |