Patent application number | Description | Published |
20080225853 | LOGICAL BRIDGING SYSTEM AND METHOD - A system and method of extending a standard bridge to enable execution of logical bridging functionality are disclosed. In some implementations, a logical bridge may assign source logical port information to a data packet based on characteristics of the data packet, employ the source logical port information to learn the source address and to forward the data packet to a logical egress port, and map the logical egress port to a physical egress port at which the data packet is to be egressed. A tunnel interface may optionally be applied to a data packet upon egress. | 09-18-2008 |
20110007744 | Packet forwarding apparatus and method - A network device includes at least one source physical port coupled to a network, and a plurality of egress ports. A logical port assignment mechanism assigns source logical port information to a data packet received via one of the at least one physical port. The source logical port information is based on characteristics of the data packet, and the source logical port information corresponds to a logical entity that is different from any source physical port. A forwarding engine determines one or more egress ports for forwarding the data packet based on at least the assigned source logical port. | 01-13-2011 |
20120106553 | PACKET FORWARDING APPARATUS AND METHOD - A network device includes at least one source physical port configured to be coupled to a network, a plurality of egress ports, and a packet processor. The packet processor includes a processing stage configured to implement a logical port assignment mechanism to assign source logical port information to a data packet received via one of the at least one source physical port, wherein the source logical port information is based on characteristics of the data packet, wherein the source logical port information corresponds to a logical entity that is different from any source physical port, and a forwarding engine to determine one or more egress ports for forwarding the data packet based on at least the assigned source logical port information. | 05-03-2012 |
20120127818 | SHARING ACCESS TO A MEMORY AMONG CLIENTS - In a memory device having a set of memory banks to store content data, at least two requests to perform respective memory operations in a first memory bank are received during a single clock cycle. One or more of the at least two requests is blocked from accessing the first memory bank, and in response: redundancy data associated with the first memory bank and different from content data stored therein is accessed, and, without accessing the first memory bank, at least a portion of the content data stored in the first memory bank is reconstructed based on the associated redundancy data. A first memory operation is performed using the content data stored in the first memory bank, and a second memory operation is performed using content data reconstructed i) without accessing the first memory bank and ii) based on the associated redundancy data. | 05-24-2012 |
20140136734 | ADAPTIVE APPARATUS - There may be provided an apparatus, that may include an input/output (IO) circuit; a micro-controller; a memory module that is arranged to store multiple type identification information and multiple type configuration information; wherein the multiple type identification information allows the apparatus to be identified as being of each one of multiple types of peripheral cards; and wherein the multiple type configuration information allows the apparatus to operate each one of the multiple types; wherein the micro-controller is arranged, following a selection of a selected type out of the multiple types: to expose, to a host—that is coupled to the apparatus, a selected portion of the multiple peripheral identification information that indicates that the apparatus has a functionality of a peripheral card of the selected type; and to configure the peripheral card to interact with the host as being a peripheral card of the selected type. | 05-15-2014 |
20140143487 | SYSTEM AND METHOD FOR MANAGING TRANSACTIONS - A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line. | 05-22-2014 |
20140310439 | LOW LATENCY INTERRUPT WITH EXISTENCE OF INTERRUPT MODERATION - A method for generating interrupt requests, the method comprising: receiving, by a first circuit, an indication of an occurrence of an interrupt triggering event; determining whether a time difference between the occurrence of the interrupt triggering event and an occurrence of a last interrupt triggering event that preceded the occurrence of the interrupt triggering event exceeded a threshold; generating, by the first circuit, an interrupt request in response to the occurrence of the interrupt triggering event if the time difference exceeded the threshold; and delaying, for a predetermined delay period after a generation of a last interrupt request, a generating of the interrupt request that is responsive to the occurrence of the interrupt triggering event if the time difference is shorter than the threshold. | 10-16-2014 |
20150120855 | HYBRID REMOTE DIRECT MEMORY ACCESS - A method for hybrid RDMA, the method may include: (i) receiving, by a first computer, a packet that was sent over a network from a second computer; wherein the packet may include data and metadata; (ii) determining, in response to the metadata, whether the data should be (a) directly written to a first application memory of the first computer by a first hardware accelerator of the first computer; or (b) indirectly written to the first application memory; (iii) indirectly writing or indirectly writing in response to the determination. | 04-30-2015 |