Patent application number | Description | Published |
20140076467 | BULK NICKEL-SILICON-BORON GLASSES BEARING CHROMIUM - Nickel based alloys capable of forming bulk metallic glass are provided. The alloys include Ni—Cr—Si—B compositions, with additions of P and Mo, and are capable of forming a metallic glass rod having a diameter of at least 1 mm. In one example of the present disclosure, the Ni—Cr—Mo—Si—B—P composition includes about 4.5 to 5 atomic percent of Cr, about 0.5 to 1 atomic percent of Mo, about 5.75 atomic percent of Si, about 11.75 atomic percent of B, about 5 atomic percent of P, and the balance is Ni, and wherein the critical metallic glass rod diameter is between 2.5 and 3 mm and the notch toughness between 55 and 65 MPa m | 03-20-2014 |
20140096873 | BULK NICKEL-PHOSPHORUS-BORON GLASSES BEARING MOLYBDENUM - The disclosure provides Ni—Mo—P—B, Ni—Mo—Nb—P—B, and Ni—Mo—Nb—Mn—P—B alloys capable of forming metallic glass objects. The metallic glass objects can have lateral dimensions in excess of 1 mm and as large as 3 mm or larger. The disclosure also provides methods for forming the metallic glasses. | 04-10-2014 |
20140116579 | BULK NICKEL-BASED CHROMIUM AND PHOSPHORUS BEARING METALLIC GLASSES WITH HIGH TOUGHNESS - A Ni-based bulk metallic glass forming alloy is provided. The alloy includes Ni | 05-01-2014 |
20140130942 | BULK IRON-NICKEL GLASSES BEARING PHOSPHORUS-BORON AND GERMANIUM - An alloy comprising Fe, Ni, P, B and Ge is disclosed, having a composition according to the formula [Fe | 05-15-2014 |
20140130945 | BULK NICKEL-PHOSPHORUS-BORON GLASSES BEARING CHROMIUM AND TANTALUM - A bulk-glass forming Ni—Cr—Nb—P—B alloy is provided. The alloy includes Ni | 05-15-2014 |
20140190593 | BULK NICKEL-SILICON-BORON GLASSES BEARING IRON - Ni—Fe—Si—B and Ni—Fe—Si—B—P metallic glass forming alloys and metallic glasses are provided. Metallic glass rods with diameters of at least one, up to three millimeters, or more can be formed from the disclosed alloys. The disclosed metallic glasses demonstrate high yield strength combined with high corrosion resistance, while for a relatively high Fe contents the metallic glasses are ferromagnetic. | 07-10-2014 |
20140202596 | MELT OVERHEATING METHOD FOR IMPROVED TOUGHNESS AND GLASS-FORMING ABILITY OF METALLIC GLASSES - A method of forming a bulk metallic glass is provided. The method includes overheating the alloy melt to a temperature above a threshold temperature, T | 07-24-2014 |
20140213384 | GOLF CLUB FABRICATED FROM BULK METALLIC GLASSES WITH HIGH TOUGHNESS AND HIGH STIFFNESS - Golf clubs formed from bulk-solidifying amorphous metals (i.e., metallic glasses) having high elastic modulus and fracture toughness, and to methods of forming the same are provided. Among other components, the golf club materials disclosed enable fabrication of flexural membranes or shells used in golf club heads (drivers, fairways, hybrids, irons, wedges and putters) exhibiting enhanced flexural or bending compliance together with the ability to deform plastically and avoid brittle fracture or catastrophic failure when overloaded under bending loads. Further, the high strength of the material and its density, comparable to that of steel, enables the redistribution of mass in the golf club while maintaining a desired overall target mass. | 07-31-2014 |
20140238551 | BULK NICKEL-PHOSPHORUS-BORON GLASSES BEARING MANGANESE - The disclosure is directed to Ni—P—B alloys bearing Mn and optionally Cr and Mo that are capable of forming a metallic glass, and more particularly metallic glass rods with diameters at least 1 mm and as large as 5 mm or larger. The disclosure is further directed to Ni—Mn—Cr—Mo—P—B alloys capable of demonstrating a good combination of glass forming ability, strength, toughness, bending ductility, and corrosion resistance. | 08-28-2014 |
20140283956 | METHODS FOR SHAPING HIGH ASPECT RATIO ARTICLES FROM METALLIC GLASS ALLOYS USING RAPID CAPACITIVE DISCHARGE AND METALLIC GLASS FEEDSTOCK FOR USE IN SUCH METHODS - The disclosure is directed to a method of forming high-aspect-ratio metallic glass articles that are substantially free of defects and cosmetic flaws by means of rapid capacitive discharge forming. Metallic glass alloys that are stable against crystallization for at least 100 ms at temperatures where the viscosity is in the range of 10 | 09-25-2014 |
20140345755 | BULK NICKEL-BASED CHROMIUM AND PHOSPHORUS BEARING METALLIC GLASSES WITH HIGH TOUGHNESS - A Ni-based bulk metallic glass forming alloy is provided. The alloy includes Ni | 11-27-2014 |
20150020929 | BULK GLASS STEEL WITH HIGH GLASS FORMING ABILITY - The present disclosure provides specified ranges in the Fe—Mo—Ni—Cr—P—C—B alloys such that the alloys are capable of forming bulk glasses having unexpectedly high glass-forming ability. The critical rod diameter of the disclosed alloys is at least 10 mm. | 01-22-2015 |
20150047755 | BULK NICKEL-PHOSPHORUS-BORON GLASSES BEARING MANGANESE, NIOBIUM AND TANTALUM - The present disclosure is directed to Ni—P—B alloys and glasses containing small fractions of Nb and Ta and optionally Mn. Over a specific range, the alloys are capable of forming bulk metallic glasses having critical casting thickness in excess of 1 mm. In one embodiment, compositions with a Mn content of between 3 and 4 atomic percent, Nb content of about 3 atomic percent, B content of about 3 atomic percent, and P content of about 16.5 atomic percent, where the balance in Ni, were capable of forming bulk metallic glass rods with diameters as large as 5 mm or larger. In another embodiment, Ni-based compositions with a Mn content of between 5 and 7 atomic percent, Ta content of between 1 and 2 atomic percent, B content of about 3 atomic percent, and P content of about 16.5 atomic percent, where the balance in Ni, were capable of forming bulk metallic glass rods with diameters as large as 5 mm or larger. | 02-19-2015 |
20150050181 | FLUXING METHOD TO REVERSE THE ADVERSE EFFECTS OF ALUMINUM IMPURITIES IN NICKEL-BASED GLASS-FORMING ALLOYS - A fluxing method is disclosed by which the melt of aluminum-contaminated Ni-based glass-forming alloys is fluxed using a fluxing agent based on boron and oxygen in order to reverse the adverse effects of aluminum impurities on the glass-forming ability and toughness. | 02-19-2015 |
20150096652 | BULK NICKEL-SILICON-BORON GLASSES BEARING IRON - Ni—Fe—Si—B and Ni—Fe—Si—B—P metallic glass forming alloys and metallic glasses are provided. Metallic glass rods with diameters of at least one, up to three millimeters, or more can be formed from the disclosed alloys. The disclosed metallic glasses demonstrate high yield strength combined with high corrosion resistance, while for a relatively high Fe contents the metallic glasses are ferromagnetic. | 04-09-2015 |
20150159240 | MELT FLUXING METHOD FOR IMPROVED TOUGHNESS AND GLASS-FORMING ABILITY OF METALLIC GLASSES AND GLASS-FORMING ALLOYS - A method of fluxing the melt of metallic glass forming alloys is provided. Alloys fluxed according to the disclosed methods demonstrate a critical rod diameter that does not vary by more than 60% when varying the melt overheating. Moreover, metallic glasses produced from alloys fluxed according to the disclosed methods demonstrate notch toughness that does not vary by more than 30% when varying the melt overheating. Furthermore, a method by which used feedstock is purified such that its toughness and glass forming ability is restored for reuse is also disclosed. Recycled feedstock purified according to the disclosed method demonstrates critical rod diameter that is at least 70% of the critical rod diameter of the as-formed alloy. Also, metallic glasses produced from recycled feedstock demonstrate notch toughness of at least 70% of the notch toughness of a metallic glass produced from the as-formed alloy. | 06-11-2015 |
20150159242 | BULK NICKEL-BASED GLASSES BEARING CHROMIUM, NIOBIUM, PHOSPHORUS AND SILICON - The disclosure is directed to Ni—Cr—P eutectic alloys bearing Nb as substitution for Cr that are capable of forming metallic glasses with critical rod diameter of at least 1 mm or more. With further minority addition of Si as replacement for P, such alloys are capable of forming metallic glasses with critical rod diameters as high as 10 mm or more. Specifically, Ni-based compositions with a Cr content of between 5 and 14 atomic percent, Nb content of between 3 and 4 atomic percent, P content of between 17.5 and 19 atomic percent, and Si content of between 1 and 2 atomic percent, were capable of forming bulk metallic glass rods with diameters as large as 6 mm or larger. | 06-11-2015 |
20150159248 | FLUXING METHODS FOR NICKEL BASED CHROMIUM AND PHOSPHORUS BEARING ALLOYS TO IMPROVE GLASS FORMING ABILITY - The disclosure is directed to Ni-based glass-forming alloys bearing Cr and P, wherein the Cr atomic concentration is greater than 7 percent and the P atomic concentration is greater than 12 percent, and methods of fluxing such alloys such that their glass-forming ability is enhanced with respect to the glass-forming ability associated with their unfluxed state. | 06-11-2015 |
20150176111 | BULK NICKEL-IRON-BASED, NICKEL-COBALT-BASED AND NICKEL-COPPER BASED GLASSES BEARING CHROMIUM, NIOBIUM, PHOSPHORUS AND BORON - Ni—Fe, Ni—Co, and Ni—Cu-based bulk metallic glass forming alloys are provided. The alloys have critical rod diameters of at least 1 mm and in some instances at least 11 mm. The alloys have composition according to Ni | 06-25-2015 |
20150197837 | METHODS FOR SHAPING HIGH ASPECT RATIO ARTICLES FROM METALLIC GLASS ALLOYS USING RAPID CAPACITIVE DISCHARGE AND METALLIC GLASS FEEDSTOCK FOR USE IN SUCH METHODS - The disclosure is directed to a method of forming high-aspect-ratio metallic glass articles that are substantially free of defects and cosmetic flaws by means of rapid capacitive discharge forming. Metallic glass alloys that are stable against crystallization for at least 100 ms at temperatures where the viscosity is in the range of 10 | 07-16-2015 |
20150240336 | BULK NICKEL-CHROMIUM-PHOSPHORUS GLASSES BEARING NIOBIUM AND BORON EXHIBITING HIGH STRENGTH AND/OR HIGH THERMAL STABILITY OF THE SUPERCOOLED LIQUID - Ni—Cr—Nb—P—B alloys and metallic glasses are provided, where Nb and B are varied such as to achieve alloys with good glass forming ability that form metallic glasses which may exhibit unexpectedly high strength and/or high thermal stability of the supercooled liquid. Specifically, the alloys of the current disclosure are capable of forming metallic glasses and have critical rod diameters of at least 3 mm, while the metallic glasses exhibit yield strength greater than 2550 MPa and stability of the supercooled liquid of at least 45° C. | 08-27-2015 |
20150267286 | BULK PLATINUM-COPPER-PHOSPHORUS GLASSES BEARING BORON, SILVER, AND GOLD - The disclosure provides Pt—Cu—P glass-forming alloys bearing at least one of B, Ag, and Au, where each of B, Ag, and Au can contribute to improve the glass forming ability of the alloy in relation to the alloy that is free of these elements. The alloys are capable of forming metallic glass rods with diameters in excess of 3 mm, and in some embodiments 50 mm or larger. The alloys and metallic glasses can satisfy platinum jewelry hallmarks PT750, PT800, PT850, and PT900. | 09-24-2015 |
20150344999 | GOLD-ALUMINUM GLASSES BEARING RARE-EARTH METALS - The disclosure provides Au—Al-Rare-Earth metallic glass-forming alloys and metallic glasses comprising various other additions including but not limited to Cu, Pd, Sn and Mg. In certain embodiments, the metallic glasses according to the disclosure satisfy the 18-Karat Gold Alloy Hallmark, and demonstrate colors that include yellow and pink/rose. | 12-03-2015 |
20160047023 | BULK NICKEL-PHOSPHORUS-SILICON GLASSES BEARING MANGANESE - The disclosure is directed to Ni—P—Si alloys bearing Mn and optionally Cr, Mo, Nb, and Ta that are capable of forming a metallic glass, and more particularly demonstrate critical rod diameters for glass formation greater than 1 mm and as large as 5 mm or larger. | 02-18-2016 |
20160060739 | BULK NICKEL-BASED CHROMIUM AND PHOSPHOROUS BEARING METALLIC GLASSES - Ni-based Cr- and P-bearing alloys that can from centimeter-thick amorphous articles are provided. Within the family of alloys, millimeter-thick bulk-glassy articles can undergo macroscopic plastic bending under load without fracturing catastrophically. | 03-03-2016 |
20160090644 | BULK NICKEL-COBALT-BASED GLASSES BEARING CHROMIUM, TANTALUM, PHOSPHORUS AND BORON - Ni—Co—Cr—Ta—P—B alloys and metallic glasses with controlled ranges are provided. The alloys demonstrate a combination of good glass forming ability, high toughness, and high stability of the supercooled liquid. The disclosed alloys are capable of forming metallic glass rods of diameters at least 3 mm and up to about 8 mm or greater. Certain alloys with good glass forming ability also have high notch toughness approaching 100 MPa m | 03-31-2016 |
Patent application number | Description | Published |
20100276753 | Threshold Voltage Adjustment Through Gate Dielectric Stack Modification - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 11-04-2010 |
20120108017 | THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 05-03-2012 |
20120169415 | SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS - A semiconductor device is disclosed. The structure includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET. | 07-05-2012 |
20130278281 | SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS - A semiconductor includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET. | 10-24-2013 |
20140191297 | STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL - A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. | 07-10-2014 |
20140252413 | SILICON-GERMANIUM FINS AND SILICON FINS ON A BULK SUBSTRATE - A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin. | 09-11-2014 |
20140377924 | STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL - A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. | 12-25-2014 |
20150255569 | FinFET FORMATION WITH LATE FIN REVEAL - A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions. | 09-10-2015 |
Patent application number | Description | Published |
20090085155 | METHOD AND APPARATUS FOR PACKAGE-TO-BOARD IMPEDANCE MATCHING FOR HIGH SPEED INTEGRATED CIRCUITS - A method of package-to-board impedance matching for high speed integrated circuits (ICs). Multiple solder balls are attached to an IC package. The IC package includes multiple conductive interconnect layers, where one of the conductive interconnect layers is coupled to one or more of the multiple solder balls. Multiple vias are coupled between different conductive interconnect layers. An inductive element is coupled between an interconnect lead and a via land in the conductive interconnect layer within the IC package. The physical layout dimensions of the inductive element are configured such that the inductive element provides an inductance value that is sufficient to offset a parasitic capacitance provided by the conductive interconnect layers and the solder balls. The inductive element may be a bond wire, an inductive interconnect, or a spiral interconnect. | 04-02-2009 |
20100073893 | MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE - Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer. | 03-25-2010 |
20110061898 | REDUCING CROSS-TALK IN HIGH SPEED CERAMIC PACKAGES USING SELECTIVELY-WIDENED MESH - One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package. | 03-17-2011 |
20110103030 | Packages and Methods for Mitigating Plating Stub Effects - Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground. | 05-05-2011 |
20110133326 | Reducing Plating Stub Reflections in a Chip Package Using Resistive Coupling - Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer. | 06-09-2011 |
20120167033 | Controlling Plating Stub Reflections In A Chip Package - Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. Embodiments include determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount; based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate; and generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width. | 06-28-2012 |
20130328645 | Plating Stub Resonance Shift with Filter Stub Design Methodology - A technique is provided to increase signal bandwidth of data processing signals by providing a plating stub as a filter using multiple line segments of different widths to filter the reflected high frequency components bouncing from the stub end toward the signal path. This stub-filter shifts the resonance point to a much higher frequency, placing that point of resonance beyond the bandwidth of interest without sacrificing a low frequency loss. Accordingly, there is provided an apparatus comprising a stub filter of a substrate, comprising a multi-segmented stub comprising a plurality of stub portions, where one of the stub portions has a different impedance than another of the stub portions. | 12-12-2013 |
20130330940 | Multi-Level Connector and Use Thereof that Mitigates Data Signaling Reflections - An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated. | 12-12-2013 |
20140075748 | Multi-Level Connector and Use Thereof that Mitigates Data Signaling Reflections - An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated. | 03-20-2014 |
20140097918 | PRINTED CIRCUIT BOARD HAVING DC BLOCKING DIELECTRIC WAVEGUIDE VIAS - A printed circuit board is disclosed. The printed circuit board includes a first signal transmission layer, a via and a second signal transmission layer. The via connects the first signal transmission layer to the second signal transmission layer. The via includes a first region made of a first dielectric material having a first dielectric constant, and a second region made of a second dielectric material having a second dielectric constant lower than the first dielectric constant. The via allows AC Component of an electro-magnetic signal to be transmitted from the first signal transmission layer to the second signal transmission layer while blocking any DC component of the electromagnetic signal. | 04-10-2014 |
20140167886 | Plating Stub Resonance Shift with Filter Stub Design Methodology - A technique is provided to increase signal bandwidth of data processing signals by providing a plating stub as a filter using multiple line segments of different widths to filter the reflected high frequency components bouncing from the stub end toward the signal path. This stub-filter shifts the resonance point to a much higher frequency, placing that point of resonance beyond the bandwidth of interest without sacrificing a low frequency loss. Accordingly, there is provided an apparatus comprising a stub filter of a substrate, comprising a multi-segmented stub comprising a plurality of stub portions, where one of the stub portions has a different impedance than another of the stub portions. | 06-19-2014 |
20140284217 | MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE - The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency. | 09-25-2014 |
20150276838 | NOISE MODULATION FOR ON-CHIP NOISE MEASUREMENT - Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator. | 10-01-2015 |
20150276840 | NOISE MODULATION FOR ON-CHIP NOISE MEASUREMENT - Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator. | 10-01-2015 |
Patent application number | Description | Published |
20080283799 | NANOWIRES-BASED TRANSPARENT CONDUCTORS - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates. | 11-20-2008 |
20080286447 | NANOWIRES-BASED TRANSPARENT CONDUCTORS - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates. | 11-20-2008 |
20100243295 | NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOF - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like. | 09-30-2010 |
20110088770 | NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOF - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like. | 04-21-2011 |
20110285019 | TRANSPARENT CONDUCTORS COMPRISING METAL NANOWIRES - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates. | 11-24-2011 |
20110297642 | NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOF - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like. | 12-08-2011 |
20140338735 | NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOF - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like. | 11-20-2014 |
Patent application number | Description | Published |
20140279750 | METHOD AND SYSTEM FOR IDENTIFYING A CLEAN ENDPOINT TIME FOR A CHAMBER - Systems and methods are provided for determining a clean endpoint time for a current run of a chamber. The clean endpoint time for the current run may be determined by determining that a chamber parameter, such as a chamber pressure, has stabilized. Historical clean endpoint time data is updated by adding the clean endpoint time for the current run of the chamber. A recommended clean endpoint time is then determined for the chamber based on the updated historical clean endpoint time data. | 09-18-2014 |
20150048862 | DETECTING ARCING USING PROCESSING CHAMBER DATA - A method and apparatus for detecting substrate arcing and breakage within a processing chamber is provided. A controller monitors chamber data, e.g., parameters such as RF signals, voltages, and other electrical parameters, during operation of the processing chamber, and analyzes the chamber data for abnormal spikes and trends. Using such data mining and analysis, the controller can detect broken substrates without relying on glass presence sensors on robots, but rather based on the chamber data. | 02-19-2015 |
20150147830 | DETECTION OF SUBSTRATE DEFECTS BY TRACKING PROCESSING PARAMETERS - A method comprising processing a substrate exposed to a plasma in a processing chamber, obtaining a metric indicative of a parameter of the plasma during the processing of the substrate, and determining a defect in the substrate by comparing the metric to a predefined criteria. | 05-28-2015 |
20150219565 | APPLICATION OF IN-LINE THICKNESS METROLOGY AND CHAMBER MATCHING IN DISPLAY MANUFACTURING - A method and apparatus for measuring the thickness of a deposited layer are disclosed herein. Devices as described herein can include a transfer chamber, one or more processing chambers each having an entrance, a loadlock chamber comprising a loadlock entrance and a loadlock exit; and an optical monitoring system comprising a plurality of optical devices positioned proximate to at least one of the entrances. Methods as described herein can include delivering a substrate with at least one deposited layer through an opening in a chamber, activating an optical monitoring system at the opening of the chamber such that the optical monitoring system performs a plurality of optical measurements of the deposited layers, delivering the optical measurements to a signal processing system and correlating the optical measurements to one or more film attributes. | 08-06-2015 |
20150221484 | DETECTION OF GROUNDING STRAP BREAKAGE - The present invention generally relates to a method for detecting the breakage of one or more grounding straps without stopping processing or opening the processing chamber for inspection. In one embodiment, a method for detecting grounding strap breakage in a processing chamber includes monitoring real-time RF related data from plasma generated in the processing chamber. The method also includes comparing the real-time RF related data with a pre-determined threshold RF related data. The method includes generating an alert if the real-time RF related data meets or exceeds the pre-determined threshold RF related data. In one embodiment, the RF related data includes RF frequency, direct current voltage, voltage peak-to-peak, and/or RF reflected power. | 08-06-2015 |
20150221563 | APPLICATION OF IN-LINE GLASS EDGE-INSPECTION AND ALIGNMENT CHECK IN DISPLAY MANUFACTURING - Methods and apparatus for determining substrate integrity and alignment are described. Devices as described herein can include a transfer chamber, one or more process chambers, a loadlock chamber a first optical device, a second optical device and a radiation source positioned outside and above an opening for the loadlock chamber. Methods as described herein can include delivering a substrate to an opening in a process chamber, activating the optical device and the radiation source and capturing a plurality of images, extracting a substrate edge pattern from the plurality of images, comparing the substrate edge pattern to an expected edge pattern to determine a level of edge variance and adjusting or stopping a process if the level of edge variance is outside of an edge variation range. | 08-06-2015 |
Patent application number | Description | Published |
20100294740 | Directed self-assembly of block copolymers using segmented prepatterns - An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls. | 11-25-2010 |
20100297847 | Method of forming sub-lithographic features using directed self-assembly of polymers - Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes. | 11-25-2010 |
20110120940 | POLYMERIC FILMS MADE FROM POLYHEDRAL OLIGOMERIC SILSESQUIOXANE (POSS) AND A HYDROPHILIC COMONOMER - A composite membrane includes a filtration membrane and a layer on a surface of the filtration membrane. The layer includes a polymer including a polyhedral oligomeric silsesquioxane (POSS) derivative with a hydrophilic moiety attached to at least one vertex thereof. A method for making a composite membrane includes applying to a surface of a filtration membrane a photopolymerizable composition including a POSS compound, a hydrophilic comonomer, and a photoinitiator. The composition is cured to form a hydrophilic layer on the filtration membrane. | 05-26-2011 |
20110120941 | COMPOSITE MEMBRANES WITH PERFORMANCE ENHANCING LAYERS - A composite membrane includes a filtration membrane with a surface; and a layer on the surface of the filtration membrane. The layer includes a polymer including a poly(ethylene glycol) moiety cross-linked with an ammonium salt or a precursor of an ammonium salt | 05-26-2011 |
20110147983 | METHODS OF DIRECTED SELF-ASSEMBLY AND LAYERED STRUCTURES FORMED THEREFROM - A method of forming a layered structure comprising a domain pattern of a self-assembled material comprises: disposing on a substrate a photoresist layer comprising a non-crosslinking photoresist; optionally baking the photoresist layer; pattern-wise exposing the photoresist layer to first radiation; optionally baking the exposed photoresist layer; and developing the exposed photoresist layer with a non-alkaline developer to form a negative-tone patterned photoresist layer comprising non-crosslinked developed photoresist; wherein the developed photoresist is not soluble in a given organic solvent suitable for casting a given material capable of self-assembly, and the developed photoresist is soluble in an aqueous alkaline developer and/or a second organic solvent. A solution comprising the given material capable of self-assembly dissolved in the given organic solvent is casted on the patterned photoresist layer, and the given organic solvent is removed. The casted given material is allowed to self-assemble while optionally heating and/or annealing the casted given material, thereby forming the layered structure comprising the domain pattern of the self-assembled given material. | 06-23-2011 |
20110209106 | METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY - A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate. | 08-25-2011 |
20120012527 | COMPOSITE MEMBRANE WITH MULTI-LAYERED ACTIVE LAYER - A polymeric membrane includes an active layer on a support. The active layer includes at least two chemically distinct crosslinked, polyamide films, and the films are crosslinked with each other at an interface. | 01-19-2012 |
20120241373 | COMPOSITE MEMBRANES AND METHODS OF PREPARATION THEREOF - A polymeric membrane includes an active layer over a support, wherein the active layer includes at least two chemically distinct polyamide films. A first one of the films is in contact with the support, and a second one of the films is not in contact with the support. The second polyamide film is crosslinked with the first polyamide film at an interface therewith, and the second polyamide film includes a structure having a side chain group including an ammonium salt. | 09-27-2012 |
20120331428 | METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY - A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate. | 12-27-2012 |
20130001153 | THIN FILM COMPOSITE MEMBRANES EMBEDDED WITH MOLECULAR CAGE COMPOUNDS - A polymeric membrane on a support, wherein the polymeric membrane includes a crosslinked polymer covalently bound to a molecular cage compound. An interfacial polymerization method for making the polymeric membrane is also disclosed. | 01-03-2013 |
20130327714 | COMPOSITE MEMBRANE WITH MULTI-LAYERED ACTIVE LAYER - A thin film composite membrane includes an active layer on a support membrane, wherein the active layer includes at least two chemically distinct first and second crosslinked polyamide film sub-layers. The first film sub-layer includes a polyamide unit; and the second film sub-layer includes a copolyamide with two chemically distinct polyamide units. The first film sub-layer is closer to the support than is the second film sub-layer. | 12-12-2013 |
20140031485 | FILTRATION MEMBRANE WITH COVALENTLY GRAFTED FOULING-RESISTANT POLYMER - A method of photo-grafting onto a separation membrane a copolymer includes at least one of: | 01-30-2014 |
20140217014 | COMPOSITE FILTRATION MEMBRANES AND METHODS OF PREPARATION THEREOF - A method comprises disposing, on a porous support membrane, an aqueous mixture comprising a crosslinkable polymer comprising a poly(meth)acrylate and/or poly(meth)acrylamide backbone, thereby forming an initial film layer, wherein the crosslinkable polymer comprises a side chain nucleophilic amine group capable of interfacially reacting with a multi-functional acid halide crosslinking agent to form a crosslinked polymer; contacting the initial film layer with a mixture comprising i) the multi-functional acid halide crosslinking agent, ii) an optional accelerator, and iii) an organic solvent, the organic solvent being a non-solvent for the crosslinkable polymer; and allowing the crosslinkable polymer to interfacially react with the crosslinking agent, thereby forming a composite filtration membrane comprising an anti-fouling selective layer comprising the crosslinked polymer. | 08-07-2014 |
20140353253 | COMPOSITE MEMBRANE WITH MULTI-LAYERED ACTIVE LAYER - A polymeric membrane includes an active layer on a support. The active layer includes at least two chemically distinct crosslinked, polyamide films, and the films are crosslinked with each other at an interface. | 12-04-2014 |
20150021262 | THIN FILM COMPOSITE MEMBRANES EMBEDDED WITH MOLECULAR CAGE COMPOUNDS - A polymeric membrane on a support, wherein the polymeric membrane includes a crosslinked polymer covalently bound to a molecular cage compound. An interfacial polymerization method for making the polymeric membrane is also disclosed. | 01-22-2015 |
20150202575 | COMPOSITE MEMBRANES AND METHODS OF PREPARATION THEREOF - A polymeric membrane includes an active layer over a support, wherein the active layer includes at least two chemically distinct polyamide films. A first one of the films is in contact with the support, and a second one of the films is not in contact with the support. The second polyamide film is crosslinked with the first polyamide film at an interface therewith, and the second polyamide film includes a structure having a side chain group including an ammonium salt. | 07-23-2015 |