Patent application number | Description | Published |
20080211057 | Semiconductor having buried word line cell structure and method of fabricating the same - Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer. | 09-04-2008 |
20090124070 | Methods of Manufacturing Semiconductor Devices Including Metal Oxide Layers - Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature. | 05-14-2009 |
20090159955 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer. | 06-25-2009 |
20090321810 | NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM - Provided is a non-volatile memory device including; a substrate having source/drain regions and a channel region between the source/drain regions; a tunneling insulating layer formed in the channel region of the substrate; a charge storage layer formed on the tunneling insulating layer; a blocking insulating layer formed on the charge storage layer, and comprising a silicon oxide layer and a high-k dielectric layer sequentially formed; and a control gate formed on the blocking insulating layer, wherein an equivalent oxide thickness of the silicon oxide layer is equal to or greater than that of the high-k dielectric layer. | 12-31-2009 |
20110199804 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND RELATED METHOD OF OPERATION - A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate. | 08-18-2011 |
20110237055 | Methods of Manufacturing Stacked Semiconductor Devices - A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer. | 09-29-2011 |
20110303970 | VERTICAL SEMICONDUCTOR DEVICES - A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively. | 12-15-2011 |
20120007165 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction. | 01-12-2012 |
20120061763 | METHODS OF FORMING NON-VOLATILE MEMORY DEVICES INCLUDING LOW-K DIELECTRIC GAPS IN SUBSTRATES AND DEVICES SO FORMED - A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer. | 03-15-2012 |
20140070300 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern. | 03-13-2014 |
20140264498 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure. | 09-18-2014 |
20150064885 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNELS AND SEMICONDUCTOR DEVICES FORMED USING SUCH METHODS - Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate. | 03-05-2015 |