Patent application number | Description | Published |
20080239553 | STORAGE APPARATUS AND HEAD POSITION DEMODULATING APPARATUS - A servo pattern demodulating system for a storage apparatus includes a processing unit which calculates an outer product and an inner product of first and second vector information items read from a servo pattern recorded on a recording medium. The processing unit calculates a tangent value of an angular difference by a division between a value of the outer product and a value of the inner product, and converts a tangent value into track position information in conformity with an approximate formula and a difference table. In the difference table, each difference between the track position information corresponding to a tangent value and a value of the approximate formula is stored. The processing unit adds up the track position information based on the approximate formula and the difference, thereby to demodulate the position offset magnitude of the head. | 10-02-2008 |
20090275291 | STORAGE DEVICE - A storage device controls transmission of test data and reception of the test data according to a protocol set for test mode upon receiving, for example, a test instruction, when a reception interface and a transmission interface are electrically connected together through a cable. The storage device verifies whether the test data transmitted from any one of a controller, a buffer, and a storage medium matches the test data received by any one of them. | 11-05-2009 |
20100049946 | PROCESSOR, COMPUTER READABLE RECORDING MEDIUM, AND STORAGE DEVICE - A processor includes: a first storage part that stores instructions of a program including sets of instruction groups, which sets are hierarchically structured; a second storage part that stores an address value of the first storage part in which an instruction to be read next is stored; a third storage part that includes storage areas respectively corresponding to hierarchical levels of the program; and a control part that executes, when an instruction read from the first storage part is a call instruction that calls a different one of the sets of instruction groups, a control to store the address value in the second storage part in one of the storage areas of the third storage part that corresponds to one of the hierarchical levels with which the different one of the sets of instruction groups being executed is associated. | 02-25-2010 |
Patent application number | Description | Published |
20110260759 | DATA SYNCHRONIZER FOR SYNCHRONIZING DATA AND COMMUNICATION INTERFACE INCLUDING THE SAME - According to one embodiment, a data hold module is configured to receive first data synchronized with a first clock signal on the basis of a second timing signal and output second data obtained by synchronizing the received first data with a second clock signal differing from the first clock signal in frequency. A reception timing generator is configured to generate a timing signal synchronized with the second clock signal as the second timing signal on the basis of a first timing signal corresponding to the first data and synchronized with the first clock signal. The reception timing generator comprises flip-flops connected in cascade. An update timing adjusting module is configured to limit the timing to update the flip-flops in value on the basis of an update enable signal synchronized with the second clock signal. | 10-27-2011 |
20120023273 | COMMAND MANAGEMENT DEVICE CONFIGURED TO STORE AND MANAGE RECEIVED COMMANDS AND STORAGE APPARATUS WITH THE SAME - According to one embodiment, a command management device includes a command buffer, a free address register and a FIFO unit with entries. The command buffer stores commands received from a host. The entries include address sections configured to store addresses of the areas in the command buffer in which the respective commands are stored. The address sections are connected together like a ring. Each of the address sections includes a substitute module configured to substitute either the free address held in the free address register or a second address stored in the address section preceding the each of the address sections for a first address stored in the each of the address sections. | 01-26-2012 |
20120151101 | INTERFACE CONTROLLER, STORAGE DEVICE, AND TIMEOUT ADJUSTMENT METHOD - According to one embodiment, an interface controller includes a first timer, a monitoring result obtaining module, a monitoring result buffer and an adjuster. The first timer measures elapsed time from a first time point when the interface controller is connected to a first host device of a plurality of host devices and detects a first timeout based on the measured elapsed time and a first timeout value. The monitoring result obtaining module obtains, as a monitoring result, a value indicative of the elapsed time measured at a second time point when a first frame is received from the first host device after the first time point and before the first timeout is detected. The monitoring result buffer stores the monitoring result obtained. The adjuster adjusts the first timeout value based on at least one monitoring result stored in the monitoring result buffer. | 06-14-2012 |