Patent application number | Description | Published |
20130046921 | METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE - A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules. | 02-21-2013 |
20130067118 | APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE - A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device. | 03-14-2013 |
20130070539 | DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION - A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application. | 03-21-2013 |
20130073754 | APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES - A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration. | 03-21-2013 |
20130102111 | STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE - A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). | 04-25-2013 |
20130117828 | DISTRIBUTED NETWORK MANAGEMENT HIERARCHY IN A MULTI-STATION COMMUNICATION NETWORK - The invention relates to a network and to a method of operating a network. The network comprises a plurality of stations each able to transmit and receive data so that the network can transmit data between stations via at least one selected intermediate station. The network further comprises a plurality of levels of stations including a first level comprising user and/or seed stations, a second level comprising auxiliary stations providing access to auxiliary networks, a third level comprising at least one location management station, and a fourth level comprising at least one authentication station. The method comprises transmitting, from or on behalf of a station on the first level requiring authentication, to an authentication station via one or more stations, an authentication request message. In response, the authentication station transmits authentication data to authenticate the station on the first level. | 05-09-2013 |
20130119542 | PACKAGE HAVING STACKED MEMORY DIES WITH SERIALLY CONNECTED BUFFER DIES - A multi-chip package has a substrate, and a plurality of memory dies stacked on the substrate. A plurality of buffer dies each has an input and an output. The input of a first buffer die is connectable to an external input. The output of a last buffer die of the plurality of buffer dies is connectable to an external output. Each of the remaining inputs and outputs is connected respectively to an output or an input of another of the plurality of buffer dies to form a serial connection between the plurality of buffer dies. Each of the memory dies is connected to one of the buffer dies, such that each buffer die is connected to its respective memory dies in parallel arrangement. A memory device having multiple serially interconnected MCPs and a controller is also described. | 05-16-2013 |
20130121096 | Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 05-16-2013 |
20130134607 | INTERPOSER FOR STACKED SEMICONDUCTOR DEVICES - A semiconductor device is disclosed, comprising a substrate having at least one substrate bonding pad. A plurality of semiconductor dies are stacked on the substrate. Each semiconductor die has at least one die bonding pad located on an active surface of the die. A plurality of interposers are each mounted on a corresponding one of the semiconductor dies. Each interposer has an aperture formed therethrough in alignment with the at least one die bonding pad. An electrical connection between the at least one die bonding pad and the at least one substrate bonding pad is formed at least in part by the interposer. The electrical connection includes at least one wire bond. | 05-30-2013 |
20130135917 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE - A method and apparatus for organizing memory for a computer system including a plurality of memory devices | 05-30-2013 |
20130137296 | A TELEPHONE OUTLET FOR IMPLEMENTING A LOCAL AREA NETWORK OVER TELEPHONE LINES AND A LOCAL AREA NETWORK USING SUCH OUTLETS - An outlet for coupling at least one data unit to digital data carried over wiring that simultaneously carry a packet-based serial digital data signal and a power signal over the same conductors. The outlet includes: a wiring connector for connecting to the wiring; a transceiver coupled to the wiring connector for transmitting and receiving packet-based serial digital data over the wiring; a LAN connector coupled to the transceiver for bi-directional packet-based data communication with at least one data unit; a bridge or a router coupled between the transceiver and the LAN connector for passing data bi-directionally between the at least one data unit and the wiring; and a single enclosure housing the above-mentioned components. The enclosure is mountable into a standard wall outlet receptacle or wall outlet opening, and the transceiver and the bridge or router are coupled to the wiring connector to be powered from the power signal. | 05-30-2013 |
20130141858 | CPU WITH STACKED MEMORY - A multi-chip package has a substrate with electrical contacts for connection to an external device. A CPU die is disposed on the substrate and is in communication with the substrate. The CPU die has a plurality of processor cores occupying a first area of the CPU die, and an SRAM cache occupying a second area of the CPU die. A DRAM cache is disposed on the CPU die and is in communication with the CPU die. The DRAM cache has a plurality of stacked DRAM die. The plurality of stacked DRAM dies are substantially aligned with the second area of the CPU die, and substantially do not overlap the first area of the CPU die. A multi-chip package having a DRAM cache disposed on the substrate and a CPU die disposed on the DRAM cache is also disclosed. | 06-06-2013 |
20130163175 | SOLID STATE DRIVE MEMORY SYSTEM - A solid-state drive architecture and arrangement for standardized disk drive form factors, PCI type memory cards and general motherboard memory. The solid-state drive architecture is modular in that a main printed circuit board (PCB) of the memory system includes a host interface connector, a memory controller, and connectors. Each connector can removably receive a memory blade, where each memory blade includes a plurality of memory devices serially connected to each other via a serial interface. Each memory blade includes a physical serial interface for providing data and control signals to a first memory device in the serial chain and for receiving data and control signals from a last memory device in the serial chain. Each memory blade can be sized in length and width to accommodate any number of memory devices on either side thereof. | 06-27-2013 |
20130169343 | USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING - In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack. | 07-04-2013 |
20130170294 | MULTIPLE-BIT PER CELL (MBC) NON-VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME - A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M-1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an M | 07-04-2013 |
20130176043 | DEVICE, METHOD AND SYSTEM FOR ESTIMATING THE TERMINATION TO A WIRED TRANSMISSION-LINE BASED ON DETERMINATION OF CHARACTERISTIC IMPEDANCE - A system and method for measuring a characteristic impedance of a transmission-line comprises transmitting energy to the line, and shortly after measuring the voltage/current involved and thus measuring the equivalent impedance. The measured characteristic impedance may then be used in order to determine the termination value required to minimize reflections. In another embodiment, the proper termination is set or measured by adjusting the termination value to achieve maximum power dissipation in the terminating device. The equivalent characteristic impedance measurement may be used to count the number of metallic conductors connected to a single connection point. This abstract is not intended to limit or construe the scope of the claims. | 07-11-2013 |
20130176061 | Delay Locked Loop Circuit and Method - A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached. | 07-11-2013 |
20130201775 | SINGLE-STROBE OPERATION OF MEMORY DEVICES - An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation. | 08-08-2013 |