Patent application number | Description | Published |
20110118155 | LIGHT-WEIGHT PROPPANT FROM HEAT-TREATED PUMICE - A process for forming a strong, low-density proppant, which process includes heating pumice particulates, or shaped agglomerates thereof, so as to form heat-treated pumice particulates, or heat-treated, shaped pumice agglomerates, having an apparent density of 2.4 or less and a crush resistance of no more than 10% fines at 4000 psi. Proppants, and well treatment fluids comprising proppants, meeting these characteristics and processes for treating subterranean formations using fluids which include such proppants are also described. | 05-19-2011 |
20130153222 | LIGHTWEIGHT HOLLOW PARTICLES FOR USE IN CEMENTING - A lightweight composite having an activated surface contains a lightweight hollow core particle having cement grains which may be adhered to the hollow core or embedded in the surface of the hollow core. The hollow core particle may be prepared from calcium carbonate and a mixture of clay, such as bentonite, and a glassy inorganic material, such as glass spheres, glass beads, glass bubbles, borosilicate glass and fiberglass. | 06-20-2013 |
Patent application number | Description | Published |
20080259334 | MULTI LAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields. | 10-23-2008 |
20100190096 | TARGET AND METHOD FOR MASK-TO-WAFER CD, PATTERN PLACEMENT AND OVERLAY MEASUREMENT AND CONTROL - A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method includes creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets, determining overlay variation between the masks, exposing and creating with one mask a first lithographic processing layer on a wafer, and exposing and creating with another mask a second lithographic processing layer on the wafer, over the first layer. The method further includes measuring the targets on the wafer at one or more of the layers, and correlating the mask and wafer measurements to distinguish mask and lithography induced components of critical dimension and overlay variation. | 07-29-2010 |
20110058170 | MULTI LAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields. | 03-10-2011 |
20110069314 | MULTILAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields. | 03-24-2011 |