Patent application number | Description | Published |
20080231499 | LOCATION TRACKING OF MOBILE PHONE USING GPS FUNCTION - A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO. | 09-25-2008 |
20080259086 | HYBRID IMAGE PROCESSING SYSTEM - The present invention provides a hybrid image processing system, which generally includes an image processing unit for receiving image data corresponding to a set of images, generating commands for processing the image data, and sending the images and the commands to an image processing unit of the hybrid image processing system. Upon receipt, the image processing unit will recognize and interpret the commands, assign and/or schedule tasks for processing the image data to a set of (e.g., special) processing engines based on the commands, and return results and/or processed image data to the image interface unit. | 10-23-2008 |
20080260296 | HETEROGENEOUS IMAGE PROCESSING SYSTEM - The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion. | 10-23-2008 |
20080260297 | HETEROGENEOUS IMAGE PROCESSING SYSTEM - The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a hybrid computing system. To this extent, a hybrid system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications on a hybrid image processing system referred to herein as an image co-processor that comprises (among other things) a plurality of special purpose engines (SPEs) that work to process multiple images in an accelerated fashion. | 10-23-2008 |
20090002151 | WIRELESS SENSOR NETWORK - A system and method for implementing a wireless sensor network. The system comprises a plurality of motes, each mote having a sensor and a wireless communication system for communicating with neighboring motes; a distributed routing table distributed amongst each of the plurality of motes; and an update system for periodically updating the distributed routing table. | 01-01-2009 |
20090060157 | CONFERENCE CALL PRIORITIZATION - An improved solution for prioritizing conference call participants is provided. In an embodiment of the invention, a method includes detecting a sound of a first conference call participant; disabling a distribution of a sound of a second conference call participant upon the detecting; and enabling the distribution of the sound of the second conference call participant after an expiration of a time period. In an embodiment, a higher priority may be assigned to a specific participant, such as the host, an administrator, or manager. | 03-05-2009 |
20090110326 | HIGH BANDWIDTH IMAGE PROCESSING SYSTEM - The present invention provides a high bandwidth image processing system, which generally includes an image processing unit having a set of servers that each have a universal operating system for receiving image data corresponding to a set of images, generating commands for processing the image data, and sending the images and the commands to an image processing unit (also having a universal operating system(s)) of the high bandwidth image processing system. Upon receipt, the image processing unit will recognize and interpret the commands, assign and/or schedule tasks for processing the image data to a set of (e.g., special) processing engines based on the commands, and return results and/or processed image data to the image interface unit. | 04-30-2009 |
20090132082 | STRIPED ON-CHIP INDUCTOR - Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters. | 05-21-2009 |
20090132582 | PROCESSOR-SERVER HYBRID SYSTEM FOR PROCESSING DATA - The present invention relates to a processor-server hybrid system that comprises (among other things) a set (one or more of servers (e.g., mainframes) and a set of front-end application optimized processors. Moreover, implementations of the invention provide a server and processor hybrid system and method for distributing and managing the execution of applications at a fine-grained level via an I/O-connected hybrid system. This method allows one system to be used to manage and control the system functions, and one or more other systems to co-processor. | 05-21-2009 |
20090132638 | SERVER-PROCESSOR HYBRID SYSTEM FOR PROCESSING DATA - The present invention relates to a server-processor hybrid system that comprises (among other things) a set (one or more) of front-end servers (e.g., mainframes) and a set of back-end application optimized processors. Moreover, implementations of the invention provide a server and processor hybrid system and method for distributing and managing the execution of applications at a fine-grained level via an I/O-connected hybrid system. This method allows one system to be used to manage and control the system functions, and one or more other systems to co-processor. | 05-21-2009 |
20090134844 | APPARATUS AND METHOD FOR RECYCLING AND REUSING CHARGE IN AN ELECTRONIC CIRCUIT - An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system. | 05-28-2009 |
20090138737 | APPARATUS, METHOD AND PROGRAM PRODUCT FOR ADAPTIVE REAL-TIME POWER AND PERFOMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS - An apparatus, method and program product for optimizing core performance and power in of a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized. | 05-28-2009 |
20090138748 | APPARATUS AND METHOD FOR MICRO PERFORMANCE TUNING OF A CLOCKED DIGITAL SYSTEM - An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency. | 05-28-2009 |
20090150555 | MEMORY TO MEMORY COMMUNICATION AND STORAGE FOR HYBRID SYSTEMS - The present invention relates to memory to memory communication and storage for hybrid systems. Under the present invention, a data stream is received on a first computing device of a hybrid system. An attempt is made to store the data stream on the first computing device up to a per stream limit and a total storage limit of the first computing device. It is then determined whether to store at least a portion of the data stream on a second computing device of the hybrid system that is in communication with the first computing device. This decision is based on the per stream limit and the total storage limit of the first computing device as well as a per stream limit and a total storage limit of the second computing device. Thereafter, the at least a portion of the data stream and a control signal are communicated to the second computing device for storage. | 06-11-2009 |
20090150556 | MEMORY TO STORAGE COMMUNICATION FOR HYBRID SYSTEMS - Under the present invention, a hybrid system having multiple computing devices and storage devices is provided. The “multiple computing devices” typically include at least one server and at least one processor, both of which include local memory. Thus, the hybrid system will typically have at least two different types of computing devices. The “multiple storage devices” are typically implemented within a storage area network, and include at least one staging storage device and at least one processed data storage device. These devices will be utilized to store incoming data streams in the event that either computing device lacks sufficient space and/or sufficient credits for transmission to another computing device. | 06-11-2009 |
20090152612 | HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN - A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance. | 06-18-2009 |
20090190601 | VIRTUAL WEB SERVICE - An improved solution for Web services is provided. In an embodiment of the invention, a method for providing a virtual Web service includes: providing a Web service gatekeeper, where the gatekeeper acts as an access point to multiple private internal enterprise environments; and then the gatekeeper receives a request for access to one, or more, of these private internal enterprise environments. | 07-30-2009 |
20090202060 | TELEPHONIC VOICE AUTHENTICATION AND DISPLAY - An improved solution for telephonic voice authentication and display is provided. A method of identifying conference call participants includes detecting a sound made by one of conference call participants; identifying this conference call participant based on the sound; and then displaying an attribute of the conference call participant to one of the other conference call participants. The attribute may include a picture, a name, and/or other information related to the identified conference call participant. | 08-13-2009 |
20090202149 | PRE-PROCESSING OPTIMIZATION OF AN IMAGE PROCESSING SYSTEM - The present approach increases bandwidth by performing at least two functions at the pre-processing level. Specifically, under the present approach, program code is structured so that the segmentation and binarization functions/modules (and optionally a blob analysis function/module) are merged into a single module to reduce memory bandwidth. In addition, each image frame is segmented into a plurality of partitions (e.g., vertical strips) to enhance the reusability of the image data in LS already fetched from main memory. Each partition is then processed by a separate one of a plurality of processing engines, thereby increasing the utilization of all processing engines and allowing the processing engines to maintain good bandwidth. | 08-13-2009 |
20090213522 | ON-CHIP ADJUSTMENT OF MIMCAP AND VNCAP CAPACITORS - One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors. | 08-27-2009 |
20090240637 | RESILIENT CLASSIFIER FOR RULE-BASED SYSTEM - A resilient classifier for using with a rule-based system is provided. A system for classifying data for a rule-based system, may include: a system(s) for generating two training data sets, one data set is generated from input data while the second data set is generated from disturbed data; a system for merging the two training data sets; and a system for training a data classifier with the merged training data sets. As a result, the classification of data becomes more accurate, including when disturbed data is encountered. | 09-24-2009 |
20090245615 | VISUAL INSPECTION SYSTEM - This solution relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a cell computing system. The invention provides a high performance machine vision system over the prior art and provides a method for executing image processing applications on a Cell and BPE3 image processing system. Moreover, implementations of the invention provide a machine vision system and method for distributing and managing the execution of image processing applications at a fine-grained level via a PCIe connected system. The hybrid system is replaced with the BPE3 and the switch is also eliminated from the prior in order to meet over 1 GB processing requirement. | 10-01-2009 |
20100064156 | VIRTUALIZATION IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. | 03-11-2010 |
20100082938 | DELEGATED VIRTUALIZATION ACROSS PHYSICAL PARTITIONS OF A MULTI-CORE PROCESSOR (MCP) - This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. Such delegation may occur across the physical boundaries. Regardless, the pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs also across physical boundaries. | 04-01-2010 |
20100082941 | DELEGATED VIRTUALIZATION IN A MULTI-CORE PROCESSOR (MCP) - The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. | 04-01-2010 |
20100082942 | VIRTUALIZATION ACROSS PHYSICAL PARTITIONS OF A MULTI-CORE PROCESSOR (MCP) - Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated. | 04-01-2010 |
20100127730 | Internal charge transfer for circuits - The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture. | 05-27-2010 |
20100131712 | PSEUDO CACHE MEMORY IN A MULTI-CORE PROCESSOR (MCP) - Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss. As such, the other L2 level cache memory units serve the original L2 cache memory unit as pseudo caches | 05-27-2010 |
20100131713 | MOUNTED CACHE MEMORY IN A MULTI-CORE PROCESSOR (MCP) - Specifically, under the present invention an available on-chip memory is coupled to another logic core or memory (e.g., cache) unit using a set of cache managers. Specifically, each cache manager is coupled to the input and output of a cache memory unit. This allows the assigned memory to become an extension of the same level cache, next level cache memory, or memory buffer. This also allows the recovery of a memory block whose logic core is not operational, and is used to improve cache memory performance of the system. It should be understood in advance the teachings herein are typically applied to a Multi-Core Processor (MCP), although this need not be the case | 05-27-2010 |
20100131716 | CACHE MEMORY SHARING IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system. | 05-27-2010 |
20100131717 | CACHE MEMORY BYPASS IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system. | 05-27-2010 |
20100207585 | RESERVING POWER FOR ELECTRONIC DEVICES - The present invention provides way to reserve power for electronic devices such as mobile devices. Specifically, under the present invention, a user can establish and/or change a setting/threshold corresponding to an amount of (battery) power available to the electronic device to be held in reserve. The setting can be a percentage of total available power (e.g., n %). Once set, this amount of power is held in reserve and is unavailable for use by the electronic device. Before to the total power available to the device is reduced to the amount of power set by the user (e.g., 1-n %), an alert will be issued. If the user wishes to use the power held in reserve, the user can input a previously established reserve power access code amount that will make the reserve power available to the electronic device. | 08-19-2010 |
20100295156 | STRUCTURE FOR SYMMETRICAL CAPACITOR - Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance. | 11-25-2010 |
20100325392 | HYBRID MULTI FUNCTION COMPONENT SYSTEM - This invention describes an apparatus, architecture, method, operating system, data network, and application program products for a hybrid digital system with multiple heterogeneous components. This invention is applied to a multiple generic microprocessor architecture s with a set (e.g., one or more cores) of controlling components and a set of groups of sub-processing components. Under this arrangement, different technology cores and functional components, such as memory, are organized in a way that different technologies can collaborate as a system. | 12-23-2010 |
20110113038 | SEARCH TERM SECURITY - As indicated above, the present invention transparently inserts search arguments/terms (referred to as noise) into a search string so that the search arguments themselves would not be clearly evident when a user is searching. The inserted noise terms are related to the underlying search terms. This would confuse a mining program and/or hacker looking for sensitive material (such as intellectual property). When the search results are returned, any “hits” resulting from noise will be removed transparently from the overall results. The insertion and removal under the present invention provides a more secure level of searching, yet is completely transparent to the end user. The inserted random search arguments are germane contextually to the search string. | 05-12-2011 |
20110119253 | SECURING SEARCH QUERIES - In general, the present invention protects actual search queries submitted to web search engines using a set (i.e., at least one) of supplemental queries (hereinafter referred to as securing search queries). As a result, collections of search queries will not form statistically stable categories, and will not disclose the search subject. Any hits resulting from securing search queries will be filtered from results that are returned to the requestor. In addition, the securing search queries can be associated with protective Internet Protocol addresses to reduce the possibility of the requestor of the actual search query to be identified. | 05-19-2011 |
20120108210 | LOCATION TRACKING OF MOBILE PHONE USING GPS FUNCTION - A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO. | 05-03-2012 |
20120117291 | COMPUTATIONALLY-NETWORKED UNIFIED DATA BUS - Embodiments of the present invention provide a computationally-networked unified data bus for a multi-processing domain architecture. Specifically, in a typical embodiment, a unified data bus is provided. A first data bus adapter (e.g., a node) is coupled to the unified data bus (e.g., a link), and a first processing domain is coupled to the first data bus adapter. In general, the first data bus adapter encapsulates, translates, and interprets data communicated between the unified data bus and the first processing domain. In addition, a second data bus adapter (e.g., a node) is coupled to the unified data bus and a second processing domain is coupled to the second data bus adapter. Similar to the first data bus adapter, the second data bus adapter encapsulates, translates, and interprets data communicated between the unified data bus and the second processing domain. Under these embodiments, the first processing domain and the second processing domain can each comprise at least one element selected from a group consisting of: memory input/outputs (I/Os), cache, heterogeneous data buses, and processors. Moreover, the first processing domain and the second processing domain can be selected from a group consisting of a heterogeneous processing domain and a hybrid processing domain. | 05-10-2012 |
20120126945 | STRONG PASSIVE AD-HOC RADO-FREQUENCY IDENTIFICATION - Embodiments of the present invention provide a strong passive ad-hoc radio-frequency identification (RFID) network (the “network). The network typically includes an RFID receiver and N quantity of RFID tags coupled to one another. For example, a network under the present invention can include an RFID reader; a first RFID tag in communication with the RFID reader; and a second RFID tag in communication with the first RFID tag. The first RFID tag and the second RFID tag will have passive capacitance to allow them to store energy and data. In this example, the first RFID tag can be enabled to behave as an RFID reader. Moreover, the first RFID tag is positioned within a first field generated by the RFID reader, while the second RFID tag being in a second field generated by the first RFID tag, the second field generated using the energy stored in the first RFID tag. This type of tag to tag coupling/communication arrangement can continue for a number of tags. Not only does this allow for communication around physical obstacles, but it allows any RFID tag to be configured to perform a synchronized reader operation with the RFID reader. | 05-24-2012 |
20120126955 | ACTIVE ENERGY HARVESTING FOR RADIO-FREQUENCY IDENTIFCATION DEVICES - In general, embodiments of the present invention provide approaches for providing power to RFID transponders. In one embodiment, the RFID transponder is powered using a magnetic field generated by power lines. In another embodiment, the RFID transponder is powered using a field generated by a wireless network. In the case of the latter, the RFID transponder acts as a member of the wireless network. In so doing, the RFID transponder is granted user rights and controls, and can control devices that are available on the network | 05-24-2012 |
20120127289 | IMAGING-BASED RADIO-FREQUENCY IDENTIFICATION TRANSPONDER - The present invention relates to an imaging-based radio-frequency identification (RFID) transponder. Specifically, the transponder includes a photo-responsive cell for capturing an image; and an analysis component. The photo-responsive cell captures images of objects. Once captured, the analysis component is configured to: determine whether the RFID transponder has sufficient power to analyze the image; analyze the image on the RFID transponder if sufficient power exists; and/or transmit data corresponding to the image to an RFID reader for analysis in the event the RFID transponder has insufficient power to analyze the image. Where quality of the image and/or performance of the transponder are less than desirous, any number of corrective approaches can be taken. For example, the setup of the transponder can be adjusted, the range readout can be reduced, the integration time per pixel of the image can be increased, etc. Moreover, the range of the RFID transponder can be increased using any of the approaches discussed in the above-incorporated patent applications. | 05-24-2012 |
20120131277 | ACTIVE MEMORY PROCESSOR SYSTEM - In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. | 05-24-2012 |
20120131284 | MULTI-CORE ACTIVE MEMORY PROCESSOR SYSTEM - In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands. | 05-24-2012 |
20120137072 | HYBRID ACTIVE MEMORY PROCESSOR SYSTEM - In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization. | 05-31-2012 |
20120153279 | SEMICONDUCTOR SENSOR RELIABILITY OPERATION - Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted. Based on the output, one or more functional blocks are modified by a control sensor component to reduce semiconductor system degredation in real-time. | 06-21-2012 |
20120153450 | SELF-ORGANIZING NETWORK WITH CHIP PACKAGE HAVING MULTIPLE INTERCONNECTION CONFIGURATIONS - In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs. | 06-21-2012 |
20120158392 | SEMICONDUCTOR SENSOR RELIABILITY - Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted. | 06-21-2012 |
20120204177 | METHOD, SYSTEM AND PROGRAM PRODUCT FOR CAPTURING CENTRAL PROCESSING UNIT (CPU) UTILIZATION FOR A VIRTUAL MACHINE - The present invention allows CPU utilization for a virtual machine (VM) to be captured from a perspective of a host. Specifically, under the present invention, a work request having a set (e.g., one or more) of jobs is received by a host and allocated to a virtual machine on a node. The work request is typically accompanied by an account identifier such as a multi-value billing code. Once the work request is allocated to a particular VM on the node, a “startacct” script is issued, and a first account record is created. Thereafter, the work request is processed and the CPU utilization needed to complete the set of jobs is monitored. Once the set of jobs is completed, an “endacct” script is issued and a second account record is created. Among other things, the second account record includes the monitored CPU utilization and the account identifier. | 08-09-2012 |
20120218079 | DYNAMIC INFORMATION RADIO-FREQUENCY IDENTIFICATION (RFID) CARD WITH BIOMETRIC CAPABILITIES - Embodiments of the present invention implement dynamic elements within a RFID card. Specifically, the embodiments update card information dynamically, using a biometric image scanner (e.g., for scanning a fingerprint passively). The scanner is activated only when a user intends to use it with a designated reader by bringing the RFID card within the reader RF field range, thus preventing unauthorized reader's RFID scan. Even if an unauthorized reader comes into contact with the RFID card, the reader cannot read the user's biometric information, unless the user holds the card for use by the reader. Thus, unauthorized biometric information scanning is effectively prevented. The medium owned and controlled by the user collects a biometric fingerprint image for safety and security. When a card is swiped by the user, the biometric imaging array sensor captures user fingerprints and transfers the corresponding image data to a verification system to match and track user biometric information with a predefine accuracy, and track changes of repeated uses. | 08-30-2012 |
20120223411 | STRIPED ON-CHIP INDUCTOR - Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters. | 09-06-2012 |
20120254500 | SYSTEM ARCHITECTURE BASED ON DDR MEMORY - Embodiments of the present invention provide an SSD system architecture based on DDR memory. Specifically, embodiments of this invention provide a set of SSD RAID controllers coupled to a system control board. Coupled to each SSD RAID controller is a set of memory control units, each of the set of memory control units include an SSD controller and a set of DRAM memory units. | 10-04-2012 |
20120254501 | SYSTEM ARCHITECTURE BASED ON FLASH MEMORY - Embodiments of the present invention provide a semiconductor storage device (SSD) system architecture based on flash memory. Specifically, embodiments of this invention provide a set of SSD RAID controllers coupled to a system control board. A set of flash memory control units coupled to each of the set of SSD RAID controllers, each of the set of flash memory control units comprising an SSD controller and a set of flash memory units. | 10-04-2012 |
20120275669 | ADAPTIVE FINGERPRINT SCANNING - Embodiments of the present invention provide an adaptive and intelligent fingerprint scanning device and approach. Specifically, embodiments of the present invention utilize DC resistive image scanning to reduce overall scanning time and energy consumption (e.g., by identifying a targeted scanning area). In a typical embodiment, a scanning device will be provided that includes a scanning area comprised of a set (e.g., at least one) of imaging pixel electrodes (e.g., arranged adjacent to one another in a grid- like or other fashion). As a user presses his/her finger against the scanning area, a first portion of the finger will contact a first electrode while a second portion of the finger will contact a second electrode. When this occurs, a voltage source of the device will apply an initial voltage across the first and second finger portions. A meter of the device will take an electrical measurement (e.g., resistance and/or charged skin voltage) across the two finger portions. Based on the electrical measurement, a location of the finger on the device will be identified, and the fingerprint will be scanned accordingly. Thus, the entire scanning surface need not be scanned, only the portions thereof where the finger was detected. | 11-01-2012 |
20120278526 | SYSTEM ARCHITECTURE BASED ON ASYMMETRIC RAID STORAGE - Embodiments of the present invention provide a semiconductor storage device (SSD) system based on asymmetric RAID storage. Specifically, embodiments of this invention provide a set of (at least one) of RAID controllers coupled to a host computer. A set of storage drives is coupled to each asymmetric RAID controller. The RAID method and configuration of each storage device are dynamically adapted based on user policy parameters and storage performance characteristics. | 11-01-2012 |
20120278527 | SYSTEM ARCHITECTURE BASED ON HYBRID RAID STORAGE - Embodiments of the present invention provide a semiconductor storage device (SSD) system based on hybrid RAID storage. Specifically, embodiments of this invention provide a set of (at least one) RAID controllers coupled to a host computer. A set of storage drives is coupled to each hybrid RAID controller. The RAID method and configuration of each storage device are dynamically adapted based on user policy parameters and storage performance characteristics. | 11-01-2012 |
20120278550 | SYSTEM ARCHITECTURE BASED ON RAID CONTROLLER COLLABORATION - Embodiments of the present invention provide a semiconductor storage device (SSD) system based on redundant array of independent disks (RAID) controller collaboration. Specifically, embodiments of the present invention provide a set (at least one) of RAID controllers coupled to a host system, wherein each of the set of RAID controllers is configured to collaborate with at least one other RAID controller within the set through at least one dedicated controller-to-controller channel to enable high bandwidth RAID storage. | 11-01-2012 |
20120280048 | AUTHORIZING THE USE OF A TRANSACTION CARD - Embodiments of the present invention provide systems and methods for validating a user of a transaction card. Specifically, embodiments of the present invention utilize dynamic manipulation of a transaction card to authorize use of the card. In a typical embodiment, the cardholder approaches a magnetic reader with the card. The card is powered up by an embedded radio frequency identification (RFID) antenna in a magnetic field. The cardholder enters a user authorization code using an input method. The entry is compared against the predefined user authorization code. If the entry is invalid, an unauthorized code is put on virtual ferromagnetic cells (VFC) embedded in the card. If the entry is valid, legitimate card information is put into the VFC. When the card is swiped, magnetic information on the VFC is coupled, amplified, and recorded to the reader. After cardholder use, the VFC are reset to a random or unauthorized mode. | 11-08-2012 |
20120280828 | RFID-BASED ELECTRICITY METERING SYSTEM - Embodiments of the present invention provide a radio frequency identification (RFID) based electricity metering system enabled to meter energy consumption of individual devices. Specifically, embodiments of this invention provide a set (a least one) of RFID sensor units, each RFID sensor unit comprising: an inductor affixed to the power line of an electronic device configured to produce an induced current using the power line of the electronic device through inductive coupling; a programmable gain amplifier (PGA) coupled to the inductor configured to provide gain or attenuation control on the induced current so that the induced current is properly scaled; an analog-to-digital converter (ADC) configured to convert the amplitude of the induced current to a digital value representing the energy consumption of the electronic device; a central processing unit (CPU) coupled to the ADC configured to receive the digital value from the ADC; a memory unit configured to store the digital value from the CPU; an antenna coupled to the CPU configured to transmit the digital value within a frequency band; and an RFID reader configured to receive the digital value transmitted by the RFID sensor unit. | 11-08-2012 |
20120286930 | AUTOMATED CARD INFORMATION EXCHANGE PURSUANT TO A COMMERCIAL TRANSACTION - In general, embodiments of the present invention relate to a card and associated methods for automated information (static and dynamic) exchange pursuant to a commercial transaction. In a typical embodiment, the card (e.g., a credit card, a debit card and/or a smart card) comprises an energy component for providing power to the card and a back display (e.g., positioned on the back or magnetic strip side of the card) for displaying card information being used in the commercial transaction. Upon display, a terminal (e.g., a point of sale terminal) will scan/read the card information and generate a corresponding source validation code (SVC). An imager positioned on the back of the card will scan/read the SVC and card validation code (CVC) logic on the card will generate a CVC based on the SVC (e.g., based on a validation result of the SVC). A biometric reader positioned on a front side of the card will take a biometric reading from a user of the card and corresponding user validation code (UVC) logic will generate a UVC based on the biometric reading. The underlying commercial transaction can then be validated (e.g., by a server associated with the terminal or by validation logic on the card itself), a validation result can be displayed on a front display (e.g., positioned on the front side of the card). | 11-15-2012 |
20120288169 | MULTI-SIDED CARD HAVING A RESISTIVE FINGERPRINT IMAGING ARRAY - Embodiments of the present invention provide an adaptive and intelligent fingerprint scanning device and approach for a multi-sided card. Specifically, embodiments of the present invention utilize DC resistive image scanning to reduce overall scanning time and energy consumption (e.g., by identifying a targeted scanning area). In a typical embodiment, a scanning device will be provided that includes a scanning area comprised of a set (e.g., at least one) of imaging pixel electrodes (e.g., arranged adjacent to one another in a grid-like or other fashion). As a user presses his/her finger against the scanning area, a first portion of the finger will contact a first electrode while a second portion of the finger will contact a second electrode. When this occurs, a voltage source of the device will apply an initial voltage across the first and second finger portions. A meter of the device will take an electrical measurement (e.g., resistance and/or charged skin voltage) across the two finger portions. Based on the electrical measurement, a location of the finger on the device will be identified, and the fingerprint will be scanned accordingly. Thus, the entire scanning surface need not be scanned, only the portions thereof where the finger was detected. | 11-15-2012 |
20120292392 | TIME-VARYING BARCODE IN AN ACTIVE DISPLAY - Embodiments of the present invention provide time-varying barcodes in an active display for information exchange. Specifically, embodiments of the present invention provide a system and method for communicating information between electronic devices via a barcode image sequence. In a typical embodiment, a barcode image sequence is displayed on the display screen of a first electronic device. A second electronic device reads and decodes the barcode image sequence. The second electronic device displays an acknowledgement on the display screen of the second electronic device. The acknowledgement is read by the first electronic device. | 11-22-2012 |
20120293847 | IMAGE ARRAY WITH LOCALIZED LIGHT SOURCE - Embodiments of the present invention provide lighting for an image array. Specifically, embodiments of the present invention provide a system and method for providing localized lighting for an image array. In a typical embodiment, a set of pixels being scanned in the image array is identified. A subset of light sources within an array of light sources that corresponds to the set of pixels is engaged. After the pixels have been scanned, the subset of light sources is disengaged. | 11-22-2012 |
20120297164 | VIRTUALIZATION IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. | 11-22-2012 |
20120298752 | TIME-VARYING BARCODES FOR INFORMATION EXCHANGE - Embodiments of the present invention provide time-varying barcodes for information exchange. Specifically, embodiments of the present invention provide a system and method for communicating information between electronic devices via a time-varying barcode image sequence. In a typical embodiment, information to be transmitted is divided into packets. A barcode image is generated from each packet. Each barcode image is displayed sequentially with varying display times based on the complexity of the barcode image. A second electronic device reads and decodes the barcode image sequence until the entire information is received. | 11-29-2012 |
20120298757 | AUTHORIZING THE USE OF A BIOMETRIC CARD - Embodiments of the present invention provide a system and method for authorizing the use of a biometric transaction card. Specifically, embodiments of the present invention provide a biometric card having a biometric sensor to determine whether the biometric information (fingerprint) is from human skin. In a typical embodiment, the cardholder approaches a magnetic reader with the card. The user places his/her finger on the SpO | 11-29-2012 |
20120318863 | LIGHT-POWERED SMART CARD FOR ON-LINE TRANSACTION PROCESSING - In general, embodiments of the present invention relate to a light-powered smart card and associated methods for automated information (static and dynamic) exchange pursuant to a commercial transaction. In a typical embodiment, the card (e.g., a credit card, a debit card and/or a smart card) comprises (among other things) an energy component for providing power to the card. Upon powering up via a light source, including light from the interfacing terminal's backlight, a terminal (e.g., a point of sale terminal) will scan/read card information shared between the card and the card company (e.g., upon swiping or placing of the card), and generate a corresponding source validation code (SVC). An optional imager/image array positioned on the back of the card will scan/read the SVC, and card validation code (CVC) logic on the card will generate a CVC based on the SVC (e.g., based on a validation result of the SVC). | 12-20-2012 |
20120319225 | DYNAMICALLY CONFIGURABLE PHOTOVOLTAIC CELL ARRAY - Embodiments of the present invention relate to photovoltaic cells. Specifically, the present invention relates to photovoltaic (PV) cells configurable for energy conversion and imaging. In a typical embodiment, each photovoltaic cell (PV) in the photovoltaic array is divided into a pixel-based array. Each photovoltaic cell is coupled to a set of switches and the photovoltaic cell is dynamically configured for energy conversion or imaging based on the settings of at least one of the switches. | 12-20-2012 |
20120321148 | MULTIPLE CHARGE-COUPLED BIOMETRIC SENSOR ARRAY - Embodiments of the present invention relate to fingerprint scanning. Specifically, the present invention relates to a multi-sided fingerprint scanning device on a card (e.g., credit card, smart card, etc.), an associated energy-efficient method for attaining accurate fingerprint information using a multiple charge-coupled biometric sensor array. In a typical embodiment, a scanning device will be provided that includes a scanning area comprised of a set (e.g., at least one) of imaging pixel electrodes (e.g., arranged adjacent to one another in a grid-like or other fashion). As a user presses his/her finger against the scanning area, a portion of the finger will contact a plurality of electrodes. When this occurs, a voltage source of the device will apply a first voltage to each of the plurality of electrodes. A meter of the device will take a first electrical measurement (e.g., resistance and/or charged skin voltage) of the plurality of electrodes. The voltage source of the device will apply a second voltage to the plurality of electrodes. The meter of the device will take a second electrical measurement (e.g., resistance and/or charged skin voltage) of the plurality of electrodes. The voltage level difference between the first electrical measurement and second electrical measurement is calculated. The voltage level difference provides accurate fingerprint information. | 12-20-2012 |
20120325905 | DYNAMIC DISPLAY INFORMATION CARD - In general, embodiments of the present invention provide a card (e.g., identification, debit card, credit card, smart card, etc.) having a dynamic information display panel integrated therein. The display panel is typically activated when user uses the card. This can occur when the card is swiped, and/or is powered up via an integrated energy panel (e.g., by an external light source). Alternatively, the card can be powered by RFID coupling, smart IC contact, battery, etc. Upon powering up, displayed information is used to: identify the user; and/or show private information to user only. Along these lines, displayed information can remain in card memory and/or on the display until next transaction, or it can be deleted after a programmed duration. | 12-27-2012 |
20130005304 | AUTHENTICATION OF A USER TO A TELEPHONIC COMMUNICATION DEVICE - The invention provides a method, system, and program product for authenticating a user to a telephonic communication device. In one embodiment, the invention includes obtaining a reference sample of an authorized user's voice, storing the reference sample of the authorized user's voice, collecting a sample of the voice of a user of the telephonic communication device, comparing the sample of the voice of the user to the reference sample of the authorized user's voice, determining whether the user is the authorized user, and in the case that the user is determined not to be the authorized user, prohibiting use of the telephonic communication device. | 01-03-2013 |
20130021086 | HIGH CAPACITY ELECTRONIC SWITCH - Embodiments of the present invention provide an electronic switch for commodity use. Specifically, embodiments of this invention provide a high capacity intelligent electronic switch for commodity use. A flexible film substrate is used along with a field-effect transistor (FET) to produce a commodity switch. Multiple printed flexible electronics PFE substrates are stacked to and integrated into an electronic switch system. Various methods are used to measure power consumption within the switch. The modular cell design allows for horizontal and vertical scaling. | 01-24-2013 |
20130054930 | METHOD, SYSTEM AND PROGRAM PRODUCT FOR STORING DOWNLOADABLE CONTENT ON A PLURALITY OF ENTERPRISE STORAGE SYSTEM (ESS) CELLS - The present invention takes advantage of unused storage space within the ESS cells to provide for the efficient and cost effective storage of downloadable content. Specifically, the system of the present invention generally includes a download grid manager that communicates with the ESS cells. Content to be replicated to the ESS cells, and characteristics corresponding thereto, are received on the download grid manager from a content owner (or the like). Based on the characteristics, a storage policy, and storage information previously received from the ESS cells, the download grid manager will replicate the downloadable content to unused storage space within the ESS cells. | 02-28-2013 |
20130066734 | TRANSACTION RECORD GENERATION AND STORAGE - Embodiments of the present invention relate to an electronic transaction and more particularly to a method for generating and storing a record of a financial transaction in an electronic format. In one embodiment, a purchaser selects data relating to the purchaser to be included in the financial transaction record. The purchaser data that is selected is retrieved, along with any additional information to be included in the financial transaction record relating to the transaction. An electronic record of the financial transaction is generated based on the retrieved data. The electronic record of the financial transaction is stored in a database. | 03-14-2013 |
20130086315 | DIRECT MEMORY ACCESS WITHOUT MAIN MEMORY IN A SEMICONDUCTOR STORAGE DEVICE-BASED SYSTEM - In general, embodiments of the present invention provide an approach for direct memory access (DMA) without main memory for a semiconductor storage device (SSD)-based system. Specifically, in a typical embodiment, an input/output hub (IOH) is provided with an inter-DMA engine. The IOH is coupled to a central processing unit (CPU), a set of double data rate (DDR) SSD memory disk units, and a graphics card. The graphics card can comprise a cache memory unit or other type of memory unit. Among other things, this embodiment provides one or more of the following features: interchangeability of hardware; resource allocation for DMA in the CPU utilizes inter-DMA resources; direct data transfer to the graphics card/processor; and/or no need to depend on a main memory comment needed in previous approaches. | 04-04-2013 |
20130086325 | DYNAMIC CACHE SYSTEM AND METHOD OF FORMATION - Embodiments of the present invention provide a dynamic cache system comprising: a multi-level inspector design that handles multi-level data formats; a cache function design that handles multi-level data formats; a cache size controller design that is able to handle the varying cache sizes based on characteristics such as hit-rates, usage patterns, etc.; a cache behavior controller design that handles different types of files; and heterogeneous storage controller design that is configured to handle volumes of the storage based on the types of storage (RAM Disk, flash, HDD, etc.). Advantages of system include (among others): caching for different types of data when different types of data need to be cached, and/or cache size can be allocated based on the cache level (which itself can be established). | 04-04-2013 |
20130104011 | SECURE ERROR DETECTION AND SYNCHRONOUS DATA TAGGING FOR HIGH-SPEED DATA TRANSFER - Embodiments of the present invention provide a system for secure error detection and synchronous data tagging for high-speed data transfer (e.g., utilizing a set of SSD memory disk units). Specifically, in a typical embodiment, the system comprises a SSD memory disk unit in communication with a device driver. A first encoded communication stream will be generated with the device driver and sent via PCI-based channel (e.g., full duplex) to the SSD memory disk unit. The stream is received, synchronized, and decoded on the SSD memory disk unit. In turn, the SSD memory disk unit can generate and send a second encoded communication steam to the device driver. | 04-25-2013 |
20130111104 | ASYNCHRONOUS DATA SHIFT AND BACKUP BETWEEN ASYMMETRIC DATA SOURCES | 05-02-2013 |
20130124822 | CENTRAL PROCESSING UNIT (CPU) ARCHITECTURE AND HYBRID MEMORY STORAGE SYSTEM - In general, embodiments of the present invention relate to CPU and/or digital memory architecture. Specifically, embodiments of the present invention relate to various approaches for adapting current CPU designs. In one embodiment, the CPU architecture comprises a storage unit coupled to a CPU and/or a memory translator but no memory unit. In another embodiment, the architecture comprises a memory unit coupled to a CPU and/or a storage mapper, but no storage unit. In yet another embodiment, the CPU can be coupled to a memory unit, a storage unit and/or a memory-to-storage mapper. Regardless, the embodiments can utilize I/O hubs, convergence I/Os and/or memory controllers to connect/couple the components to one another. In addition, a tag can be provided for the memory space. The tag can include fields for a virtual header length, a virtual address header, and/or a physical address. | 05-16-2013 |
20130138976 | PROCESSOR, CONTROLLER, AND INPUT/OUTPUT DEVICE POWER REDUCTION AND OPTIMIZATION - Embodiments of the present invention provide a processor design that enables controller and I/O device power reduction and optimization. In a typical embodiment, a processing core is coupled to a set (e.g., three) of I/O blocks. The processing core provides for selective activation and/or deactivation of any of the I/O blocks. Two of the I/O blocks are coupled to individual voltage I/O components as well as individual external circuits. In one embodiment, the individual external circuits are coupled to individual voltage control components. | 05-30-2013 |
20130151766 | CONVERGENCE OF MEMORY AND STORAGE INPUT/OUTPUT IN DIGITAL SYSTEMS - Embodiments of the present invention relate to CPU and/or digital memory architecture. Specifically, embodiments of the present invention relate to various approaches for adapting current designs to provide connection of a storage unit to a CPU via a memory unit through the use of controllers. This allows for system data to flow from the CPU to the memory unit to the storage unit. Such a configuration is enabled by the use of an extended memory access scheme that comprises a plurality of row address strobes (RAS) and a column address strobe (CAS) (and, optionally, one or more data bit line DQs). | 06-13-2013 |
20130227222 | MULTI-CORE ACTIVE MEMORY PROCESSOR SYSTEM - In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands. | 08-29-2013 |
20130237155 | MOBILE DEVICE DIGITAL COMMUNICATION AND AUTHENTICATION METHODS - Embodiments of the present invention provide various approaches for mobile device intercommunication (e.g., digital) as well as various authentication methods. In one embodiment, the present invention provides direct line-of-sight visual digital communication between mobile devices for controlled security. In another embodiment, the present invention provides direct contact motion-based digital communication between mobile devices for controlled security. Embodiments of the present invention also provide various authentication methods. One such example relates to secure authentication code exchange with subsequent digital communications in one or more channels. In another example, human-readable information is used along machine-readable digital codes (e.g., quick response (QR) codes to verify visual codes. Still yet, embodiments of the present invention provide non-obtrusive visual codes that maintain a user's access to a mobile device screen. | 09-12-2013 |
20130275687 | MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION - Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system. | 10-17-2013 |
20130290605 | CONVERGED MEMORY AND STORAGE SYSTEM - Embodiments of the present invention provide an approach for Dynamic Random Access Memory (DRAM) and flash converged memory and storage. Specifically, in a typical embodiment, at least one substrate will be provided on which a DRAM unit and flash memory unit are positioned. A set (e.g., one or more of input/outputs (I/Os)) may be provided for the units. Such a set of I/Os may communicate storage and/or memory access requests to a set (e.g., one or more) of controllers, which control the DRAM and flash memory units. The set of controllers may comprise a single integrated controller or multiple controllers having separate and distinct functions (e.g., a memory controller, a storage controller, a DRAM controller, a flash controller, etc.). | 10-31-2013 |
20130294661 | AUTHORIZING THE USE OF A BIOMETRIC CARD - Embodiments of the present invention provide a system and method for authorizing the use of a biometric transaction card. Specifically, embodiments of the present invention provide a biometric card having a biometric sensor to determine whether the biometric information (fingerprint) is from human skin. In a typical embodiment, the cardholder approaches a magnetic reader with the card. The user places his/her finger on the SpO | 11-07-2013 |
20130322147 | LEAKAGE AND PERFORMANCE GRADED MEMORY - Embodiments of the present invention provide a memory configuration on a chip containing multiple memory segments having different memory grades. In a typical embodiment, a single chip will be provided on which the memory segments are positioned. A memory grade may include low performance (low leakage), medium performance (medium leakage), and high performance (high leakage). Each memory segment or group of memory segments may have a separate power supply and/or controller. In one example, memory segments may be stacked in a through-silicon via configuration. | 12-05-2013 |
20140025972 | ADAPTIVE REAL-TIME POWER AND PERFORMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS - An apparatus, method, and program product for optimizing core performance and power in a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized. | 01-23-2014 |
20140072112 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR CONTACTING CONFERENCE CALL PARTICIPANTS - The present invention provides a method, system, and program product for managing conference calls. Specifically, prospective conference call participants (e.g., moderators and/or invitees) will initially provide user profiles. A participant's profile will include, among other things, a set of contact numbers at which the participant can be reached. Thereafter, a moderator and a set of invitees of a conference call to be held are identified. This is typically done based on synchronization with a calendar application used to send and accept an invitation to the conference call. When the moderator later initiates the conference call, the present invention will access the profile of each invitee that accepted the invitation, and then call the invitees at the respective contact numbers set forth therein. When contact is made with an invitee, the call will be merged into the conference call with the moderator. | 03-13-2014 |
20140072113 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR CONTACTING CONFERENCE CALL PARTICIPANTS - The present invention provides a method, system, and program product for managing conference calls. Specifically, prospective conference call participants (e.g., moderators and/or invitees) will initially provide user profiles. A participant's profile will include, among other things, a set of contact numbers at which the participant can be reached. Thereafter, a moderator and a set of invitees of a conference call to be held are identified. This is typically done based on synchronization with a calendar application used to send and accept an invitation to the conference call. When the moderator later initiates the conference call, the present invention will access the profile of each invitee that accepted the invitation, and then call the invitees at the respective contact numbers set forth therein. When contact is made with an invitee, the call will be merged into the conference call with the moderator. | 03-13-2014 |
20140072114 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR CONTACTING CONFERENCE CALL PARTICIPANTS - The present invention provides a method, system, and program product for managing conference calls. Specifically, prospective conference call participants (e.g., moderators and/or invitees) will initially provide user profiles. A participant's profile will include, among other things, a set of contact numbers at which the participant can be reached. Thereafter, a moderator and a set of invitees of a conference call to be held are identified. This is typically done based on synchronization with a calendar application used to send and accept an invitation to the conference call. When the moderator later initiates the conference call, the present invention will access the profile of each invitee that accepted the invitation, and then call the invitees at the respective contact numbers set forth therein. When contact is made with an invitee, the call will be merged into the conference call with the moderator. | 03-13-2014 |
20140075119 | HYBRID ACTIVE MEMORY PROCESSOR SYSTEM - In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization. | 03-13-2014 |
20140117074 | TIME-VARYING BARCODE IN AN ACTIVE DISPLAY - Embodiments of the present invention provide time-varying barcodes in an active display for information exchange. Specifically, embodiments of the present invention provide a system and method for communicating information between electronic devices via a barcode image sequence. In a typical embodiment, a barcode image sequence is displayed on the display screen of a first electronic device. A second electronic device reads and decodes the barcode image sequence. The second electronic device displays an acknowledgement on the display screen of the second electronic device. The acknowledgement is read by the first electronic device. | 05-01-2014 |
20140158761 | LIGHT-POWERED SMART CARD FOR ON-LINE TRANSACTION PROCESSING - In general, embodiments of the present invention relate to a light-powered smart card and associated methods for automated information (static and dynamic) exchange pursuant to a commercial transaction. In a typical embodiment, the card (e.g., a credit card, a debit card and/or a smart card) comprises (among other things) an energy component for providing power to the card. Upon powering up via a light source, including light from the interfacing terminal's backlight, a terminal (e.g., a point of sale terminal) will scan/read card information shared between the card and the card company (e.g., upon swiping or placing of the card), and generate a corresponding source validation code (SVC). An optional imager/image array positioned on the back of the card will scan/read the SVC, and card validation code (CVC) logic on the card will generate a CVC based on the SVC (e.g., based on a validation result of the SVC). | 06-12-2014 |
20140223110 | ACTIVE MEMORY PROCESSOR SYSTEM - In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. | 08-07-2014 |
20140333537 | POINTING DEVICE WITH INTEGRATED KEYBOARD - A pointing device/mouse having a keypad integrated thereon. Other embodiments relate to a pointing device/mouse having a virtual keypad activation mechanism, which, when activated, causes a virtual keyboard to appear on a computer screen of a tablet or similar device. | 11-13-2014 |
20140353389 | DYNAMIC INFORMATION RADIO-FREQUENCY IDENTIFICATION (RFID) CARD WITH BIOMETRIC CAPABILITIES - Embodiments of the present invention implement dynamic elements within a RFID card. Specifically, the embodiments update card information dynamically, using a biometric image scanner (e.g., for scanning a fingerprint passively). The scanner is activated only when a user intends to use it with a designated reader by bringing the RFID card within the reader RF field range, thus preventing unauthorized reader's RFID scan. Even if an unauthorized reader comes into contact with the RFID card, the reader cannot read the user's biometric information, unless the user holds the card for use by the reader. Thus, unauthorized biometric information scanning is effectively prevented. The medium owned and controlled by the user collects a biometric fingerprint image for safety and security. When a card is swiped by the user, the biometric imaging array sensor captures user fingerprints and transfers the corresponding image data to a verification system to match and track user biometric information with a predefine accuracy, and track changes of repeated uses. | 12-04-2014 |