Montanini
Pietro Montanini, Milan IT
Patent application number | Description | Published |
---|---|---|
20100075484 | SOI DEVICE WITH CONTACT TRENCHES FORMED DURING EPITAXIAL GROWING - A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material. | 03-25-2010 |
Pietro Montanini, Milano (mi) IT
Patent application number | Description | Published |
---|---|---|
20090152733 | DEEP CONTACTS OF INTEGRATED ELECTRONIC DEVICES BASED ON REGIONS IMPLANTED THROUGH TRENCHES - An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow. | 06-18-2009 |
20130017676 | DEEP CONTACTS OF INTEGRATED ELECTRONIC DEVICES BASED ON REGIONS IMPLANTED THROUGH TRENCHES - An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow. | 01-17-2013 |
Pietro Montanini, Cornaredo IT
Patent application number | Description | Published |
---|---|---|
20090136237 | Coupling structure for optical fibres and process for making it - A coupling structure for coupling optical radiation, i.e., light, between an optical fibre and an optical device, e.g., a laser diode or a photodiode. The coupling structure has an optical through-via which guides the optical radiation to or from the optical fibre. Light exiting the fibre travels through a guidance channel so it remains substantially confined to a narrow optical path that mimics the fibre core. Conversely, light enters the fibre after having traveled through the guidance channel. The guidance channel has a first core region, the “channel core”, having first refractive index surrounded by a second region, the “channel cladding” having a second refractive index smaller than the first refractive index. The coupling structure, including the guidance channel, is preferably made of semiconductor-based material, more preferably of silicon-based material. The guidance channel is preferably silicon oxide. The coupling structure further has a fibre drive-in element, which facilitates insertion and alignment of the optical fibre to the guidance channel. | 05-28-2009 |
Pietro Montanini, Milano IT
Patent application number | Description | Published |
---|---|---|
20120228260 | PROCESS FOR ETCHING TRENCHES IN AN INTEGRATED OPTICAL DEVICE - The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material. | 09-13-2012 |
Pietro Montanini, Albany, NY US
Patent application number | Description | Published |
---|---|---|
20140175609 | PRECISION POLYSILICON RESISTORS - Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both. | 06-26-2014 |
20140353741 | BOTTLED EPITAXY IN SOURCE AND DRAIN REGIONS OF FETS - A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions. | 12-04-2014 |