Patent application number | Description | Published |
20090006793 | Method And Apparatus To Enable Runtime Memory Migration With Operating System Assistance - In a method for switching to a spare memory module during runtime, a processing system determines that utilization of an active memory module in the processing system should be discontinued. The processing system may then activate a mirror copy mode that causes a memory controller in the processing system to copy data from the active memory module to the spare memory module when the data is accessed in the active memory module. An operating system (OS) in the processing system may then access data in the active memory module to cause the memory controller to copy data from the active memory module to the spare memory module. The processing system may then reconfigure the memory controller to direct reads and writes to the spare memory module instead of the active memory module. Other embodiments are described and claimed. | 01-01-2009 |
20090007121 | Method And Apparatus To Enable Runtime Processor Migration With Operating System Assistance - In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed. | 01-01-2009 |
20090067618 | Random number generator - Systems, methods, and other embodiments associated with random number generators are described. One system embodiment includes a random number generator logic that may produce an initial random number from a first set of three inputs. The system embodiment may receive the three inputs from sources including an internal counter entropy source (ICES), an internal arbitrary entropy source (IAES), and an external entropy source (EES). The system embodiment may generate a first random number from a first set of three inputs (e.g., value from ICES, value from IAES, value from EES) but may then generate subsequent random numbers from a different set of three inputs (e.g., value from ICES, value from IAES, previous random number). | 03-12-2009 |
20090086981 | Methods and Apparatus for Batch Bound Authentication - A processing system may include a processing unit and nonvolatile storage responsive to the processing unit. The nonvolatile storage may include a candidate boot code module and an authentication code module. The processing unit may be configured to execute code from the authentication code module before executing code from the candidate boot code module. The authentication code module may have instructions which, when executed by the processing unit, cause the processing unit to read a processor identifier from the processing unit and determine whether the processor belongs to a predetermined set of processors associated with a specific vendor, based at least in part on the identifier, before executing any instructions from the candidate boot code module. The processing system may also test authenticity of the candidate boot code module before executing any instructions from the candidate boot code module. Other embodiments are described and claimed. | 04-02-2009 |
20090106471 | APPARATUS AND METHOD FOR ENUMERATION OF PROCESSORS DURING HOT-PLUG OF A COMPUTE NODE - An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node. | 04-23-2009 |
20090172372 | METHODS AND APPARATUS FOR GENERATING SYSTEM MANAGEMENT INTERRUPTS - A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed. | 07-02-2009 |
20090172385 | ENABLING SYSTEM MANAGEMENT MODE IN A SECURE SYSTEM - Apparatuses, methods, and systems for enabling system management mode in a secure system are disclosed. In one embodiment, a processor includes sub-operating-system mode logic, virtual machine logic, and control logic. The sub-operating-system mode logic is to support a sub-operating-system mode. The virtual machine logic is to support virtualization. The control logic is to prevent virtualization from being enabled when the sub-operating-system mode is disabled. | 07-02-2009 |
20090249050 | SYSTEM AND METHOD FOR ESTABLISHING A TRUST DOMAIN ON A COMPUTER PLATFORM - Embodiments of the invention provide systems and methods associated with a measurement engine in a server platform. In one such embodiment of the invention, the measurement engine hardware verifies/authenticates its own firmware and then system initialization firmware by measuring such firmware and storing measurement results in a register that is not spoofable by malicious code. In this instance, the measurement engine holds the host CPU complex in a reset state until the measurement engine has verified the system initialization firmware. In another such embodiment of the invention, the measurement engine hardware also measures firmware associated with one or more system service processors and stores such measurement results in a register. In this case, the measurement engine holds the system service processors and the host CPU complex in reset until the measurements are completed. Other embodiments are described. | 10-01-2009 |
20100169729 | ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH DEFECTIVE MEMORY DEVICES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for enabling an integrated memory controller to transparently work with defective memory devices. In some embodiments, a marginal condition is imposed on a memory module during normal operations of the memory module. The term “marginal condition” refers to a condition that is out of compliance with a specified (or “normal”) operating condition for the memory module. The memory module may exhibit failures in response to the marginal conditions and compensating mechanisms may mitigate the failures. | 07-01-2010 |
20110055469 | Providing State Storage In A Processor For System Management Mode - In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed. | 03-03-2011 |
20110161592 | Dynamic system reconfiguration - In some embodiments system reconfiguration code and data to be used to perform a dynamic hardware reconfiguration of a system including a plurality of processor cores is cached and any direct or indirect memory accesses during the dynamic hardware reconfiguration are prevented. One of the processor cores executes the cached system reconfiguration code and data in order to dynamically reconfigure the hardware. Other embodiments are described and claimed. | 06-30-2011 |
20110161676 | ENTERING A SECURED COMPUTING ENVIRONMENT USING MULTIPLE AUTHENTICATED CODE MODULES - Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a processor includes a decoder and control logic. The decoder is to decode a secured enter instruction. The control logic is to find an entry corresponding to the processor in a match table in a master authenticated code module and to read a master header and an individual authenticated code module from the master authenticated code module in response to decoding the secured enter instruction. | 06-30-2011 |
20110179311 | INJECTING ERROR AND/OR MIGRATING MEMORY IN A COMPUTING SYSTEM - In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed. | 07-21-2011 |
20120265998 | Methods And Apparatus For Authenticating Components Of Processing Systems - When a processing system boots, it may retrieve an encrypted version of a cryptographic key from nonvolatile memory to a processing unit, which may decrypt the cryptographic key. The processing system may also retrieve a predetermined authentication code for software of the processing system, and the processing system may use the cryptographic key to compute a current authentication code for the software. The processing system may then determine whether the software should be trusted, by comparing the predetermined authentication code with the current authentication code. In various embodiments, the processing unit may use a key stored in nonvolatile storage of the processing unit to decrypt the encrypted version of the cryptographic key, a hashed message authentication code (HMAC) may be used as the authentication code, and/or the software to be authenticated may be boot firmware, a virtual machine monitor (VMM), or other software. Other embodiments are described and claimed. | 10-18-2012 |
20130103938 | Reconfiguring A Secure System - Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock. | 04-25-2013 |
20130151930 | Injecting A Data Error Into A Writeback Path To Memory - In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed. | 06-13-2013 |
20130212406 | TECHNIQUE FOR PROVIDING SECURE FIRMWARE - A technique to verify firmware. One embodiment of the invention uses a processor's micro-code to verify a system's firmware, such that the firmware can be included in a trusted chain of code along with the operating system. | 08-15-2013 |
20130212672 | EXECUTION OF A SECURED ENVIRONMENT INITIALIZATION INSTRUCTION ON A POINT-TO-POINT INTERCONNECT SYSTEM - Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction. | 08-15-2013 |
20130212673 | ENTERING A SECURED COMPUTING ENVIRONMENT USING MULTIPLE AUTHENTICATED CODE MODULES - Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a processor includes a decoder and control logic. The decoder is to decode a secured enter instruction. The control logic is to find an entry corresponding to the processor in a match table in a master authenticated code module and to read a master header and an individual authenticated code module from the master authenticated code module in response to decoding the secured enter instruction. | 08-15-2013 |
20130275682 | APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY OVER COMMON MEMORY CHANNELS - A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” | 10-17-2013 |
20130275810 | METHOD AND APPARATUS FOR INJECTING ERRORS INTO MEMORY - Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory. | 10-17-2013 |
20130290759 | ENHANCED SYSTEM SLEEP STATE SUPPORT IN SERVERS USING NON-VOLATILE RANDOM ACCESS MEMORY - A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM. | 10-31-2013 |
20130326288 | PROCESSOR THAT DETECTS WHEN SYSTEM MANAGEMENT MODE ATTEMPTS TO REACH PROGRAM CODE OUTSIDE OF PROTECTED SPACE - A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting. | 12-05-2013 |
20130332781 | RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS - Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor. | 12-12-2013 |
20130339829 | Machine Check Summary Register - In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view. | 12-19-2013 |
20140006597 | METHOD, SYSTEM, AND DEVICE FOR MANAGING SERVER HARDWARE RESOURCES IN A CLOUD SCHEDULING ENVIRONMENT | 01-02-2014 |
20140040543 | Providing State Storage in a Processor for System Management Mode - In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed. | 02-06-2014 |
20140129767 | APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY - A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” | 05-08-2014 |
20140143577 | POWER CONSERVATION BY WAY OF MEMORY CHANNEL SHUTDOWN - A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown. | 05-22-2014 |
20140181576 | MEMORY ALLOCATION FOR VIRTUAL MACHINES USING MEMORY MAP - Apparatuses and methods associated with memory allocations for virtual machines are disclosed. In embodiments, an apparatus may include a processor; a plurality of memory modules; and a memory controller configured to provide a layout of the memory modules. The apparatus may further include a VMM configured to be operated by the processor to manage execution of a VM by the processor including selective allocation of the memory modules to the VM using the layout of the memory modules provided to the VMM by the memory controller. Other embodiments may be described and claimed. | 06-26-2014 |
20140188829 | TECHNOLOGIES FOR PROVIDING DEFERRED ERROR RECORDS TO AN ERROR HANDLER - Technologies to generate an error record are described herein. A method includes performing a scan of one or more error logs to identify a source of data in response to an attempt to access the data, determining whether an amount of time to complete the scan will exceed a threshold value, and generating a notice that the error record will be deferred based on the determination. A system includes a data collector to scan one or more error logs to identify a source of data in response to an attempt to access the data, a controller to determine whether an amount of time to scan the error logs to identify the source of data will exceed a threshold value, and a signal generator to generate a signal indicating that the error record is to be deferred based on the determination. | 07-03-2014 |
20140189445 | SIGNALING SOFTWARE RECOVERABLE ERRORS - Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator. | 07-03-2014 |
20140195876 | Memory Module Architecture - In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments. | 07-10-2014 |
20140223226 | APPARATUS AND METHOD FOR DETECTING AND RECOVERING FROM DATA FETCH ERRORS - An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage. | 08-07-2014 |
20140237299 | SECURE ERROR HANDLING - Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed. | 08-21-2014 |
20140281092 | SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS - Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed. | 09-18-2014 |
20140297919 | APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY - A system and method are described for intelligently flushing data from a processor cache. For example, a system according to one embodiment of the invention comprises: a processor having a cache from which data is flushed, the data associated with a particular system address range; and a PCM memory controller for managing access to data stored in a PCM memory device corresponding to the particular system address range; the processor determining whether memory flush hints are enabled for the specified system address range, wherein if memory flush hints are enabled for the specified system address range then the processor sending a memory flush hint to a PCM memory controller of the PCM memory device and wherein the PCM memory controller uses the memory flush hint to determine whether to save the flushed data to the PCM memory device. | 10-02-2014 |
20140298140 | APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY - An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core. | 10-02-2014 |
20140325638 | COMPUTING DEVICE SECURITY - Techniques for providing security for a computing device are described herein. In one example, a maintenance issue for the computing device is detected. Additionally: a maintenance credential proximate the computing: device can be detected. Furthermore, an alarm system within the computing device can be disabled in response to detecting an authorized maintenance credential. | 10-30-2014 |
20150089287 | EVENT-TRIGGERED STORAGE OF DATA TO NON-VOLATILE MEMORY - An event management resource monitors a processor environment. In response to detecting occurrence of a trigger event in the processor environment, the event management resource initiates a transfer of processor cache data from volatile storage in the processor environment to non-volatile memory. The event management resource can be configured to produce status information associated with the transfer of cache data to a respective non-volatile memory resource. The event management resource stores the status information in a non-volatile storage resource for later retrieval. Accordingly, status information associated with the event causing the transfer is available for analysis on subsequent power up or reboot of a respective computer system. | 03-26-2015 |