Patent application number | Description | Published |
20080206480 | Radiation Curable Powder Coating Compositions - The present invention relates to powder compositions curable by ultraviolet irradiation or by accelerated electron beams. These powder compositions comprise at least one ethylenically unsaturated resin, and lend to the production of paint and varnish coatings exhibiting a unique combination of properties, inter alia good flow and mechanical properties and above all outstanding adhesion to metal substrates, persisting on ageing. | 08-28-2008 |
20080286481 | Thermosetting powder compositions for coatings - The present invention relates to an isophthalic acid rich carboxyl functionalized polyester, containing linear chain aliphatic (poly)ether diols, and to thermosetting powder compositions comprising a mixture of the polyester with a beta-hydroxylkylamide group containing cross-linking agent. The invention also relates to the use of said compositions for the preparation of powdered paints and varnishes for the making of coatings and to coating obtained therewith. | 11-20-2008 |
20100310801 | POWDER COMPOSITION - There is described a powder coating composition suitable for food contact use comprising a mix of: (A) a first polyester that is amorphous and COOH functional being obtained from IPA and/or TPA and no more than 10 mole % neopentyl glycol (NPG); (B) a second optional COOH functional polyester obtained from analiphatic diacid and analiphatic diol, and (C) a curing agent that comprises functional groups reactable with the COOH of the polyester(s). The powders are suitable for coating the interior of metal cans especially those holding alcoholic beverages. | 12-09-2010 |
20110166286 | POLYMER COMPOSITIONS - There is described a powder composition curable by radiation and thermally, comprising a mixture of (a) from about 1% to about 15%, by weight of the mixture, of a polyester of T | 07-07-2011 |
20120107629 | LOW TEMPERATURE CURE POWDER COATING COMPOSITIONS - The present invention relates to a powder coating composition for low temperature cure which comprises a mixture of a carboxylic acid group containing first polyester; at least one of a second polyester having a glass transition temperature ≦45° C. and/or a crystalline polycarboxylic acid; a glycidyl group containing acrylic copolymer; a further compound and/or resin having functional groups readable with the carboxylic acid groups; and a thermosetting curing catalyst. These thermosetting powder coatings are designed for coating heat-sensitive substrates such as wood, fibre board and other materials which can not withstand the excessive heat/time conditions necessary to cure traditional coatings. The powder coatings of the invention, when cured at temperatures below 150° C., produce a finish which exhibits a high gloss, smooth surface along with an outstanding hardness and weatherability. | 05-03-2012 |
20120220676 | POLYESTERS FOR COATINGS - The present invention relates to polyesters that can be prepared from renewable resources and/or recycled materials, to their use and their production process. In particular there are provided hydroxyl-functional or carboxyl-functional polyesters comprising moieties of (e) terephthalic acid and/or isophthalic acid, (f) ethylene glycol, (g) a dianhydrohexitol, and of (h) one or more linear chain dicarboxylic acids; wherein the polyester has a number average molecular weight, as measured by gel permeation chromatography, of from 400 to 15000 daltons, more preferably from 550 to 15000 daltons. Polyesters of the invention can basically be prepared from recycled polyethylene terephthalate and from renewable polyacids and/or polyols. The present invention further provides a process to produce such polyesters via glycolysis of a polyethylene terepthalate and/or a polyethylene isophthalate with a dianhydrohexitol. | 08-30-2012 |
20120270055 | COATINGS FOR CERAMIC SUBSTRATES - A process for making highly mechanical and chemical resistant ceramic substrates, especially tiles is provided, wherein the process comprises coating said substrates with a base coat layer of a thermosetting or radiation curable powder coating composition, curing the applied powder coating composition, and applying a further layer of a liquid coating composition and curing the composition by exposure to heat. Coated ceramic substrates, in particular tiles are also provided. | 10-25-2012 |
20140287242 | FLUORINATED WATER-OIL REPELLENCY AGENTS - The present invention relates to an active energy ray curable compound (A) comprising: at least one active energy ray curable group, at least one fluorine-containing moiety (a1) and at least one moiety (a2) comprising at least one portion represented by Formula (1): —[C(═O)—CH(R)—O—C(═O)—CH(R)—O]n- wherein n is an integer from 1 to 10, and wherein R is selected from —H or —CH | 09-25-2014 |
Patent application number | Description | Published |
20080290461 | DEEP TRENCH ISOLATION FOR POWER SEMICONDUCTORS - An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the reverse breakdown voltage characteristics such as voltage level, reliability and stability can be improved for a given area of device, or for a given complexity of device, and avalanche breakdown at weaknesses in isolation structures can be reduced or avoided. | 11-27-2008 |
20090014785 | SEMICONDUCTOR DEVICE WITH IMPROVED BREAKDOWN PROPERTIES AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device ( | 01-15-2009 |
20090039460 | DEEP TRENCH ISOLATION STRUCTURES IN INTEGRATED SEMICONDUCTOR DEVICES - A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic. | 02-12-2009 |
20090268357 | Hybrid ESD Clamp - A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode ( | 10-29-2009 |
20100065908 | ALIGNMENT OF TRENCH FOR MOS - Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced. | 03-18-2010 |
20100105188 | DOUBLE TRENCH FOR ISOLATION OF SEMICONDUCTOR DEVICES - Semiconductor device has a substrate ( | 04-29-2010 |
20100140698 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described. | 06-10-2010 |
20110156141 | TRANSISTOR AND METHOD THEREOF - An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions. | 06-30-2011 |
20120187526 | METHOD OF FORMING A SEMICONDUCTOR DEVICE TERMINATION AND STRUCTURE THEREFOR - At least one exemplary embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several conductivity layers and a buffer layer. | 07-26-2012 |
20120187527 | METHOD OF FORMING A SEMICONDUCTOR DEVICE TERMINATION AND STRUCTURE THEREFOR - At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer. | 07-26-2012 |
20140097489 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region. | 04-10-2014 |
20140097517 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, UIS performance. | 04-10-2014 |
20140103421 | SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - In one embodiment, the semiconductor devices relate to using one or more super junction trenches for termination. | 04-17-2014 |
20140264367 | HEMT Semiconductor Device and a Process of Forming the Same - A HEMT semiconductor device can include a dielectric layer that includes a silicon nitride film and an AlN film. In an embodiment, the HEMT semiconductor device can include a GaN film and an AlGaN film. In a process of forming the HEMT device, the AlN can provide an etch stop when forming an opening for a gate electrode. | 09-18-2014 |
20140264368 | Semiconductor Wafer and a Process of Forming the Same - A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate. | 09-18-2014 |
20140264453 | METHOD OF FORMING A HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions of the HEM device. | 09-18-2014 |
20140264454 | OHMIC CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD - In one embodiment, a high electron mobility device structure includes heterostructure with a Group III-nitride channel layer and a Group III-nitride barrier layer that forms a two-dimensional electron gas layer at an interface between the two layers. At least one current carrying electrode includes a recess-structured conductive contact adjoining and making Ohmic contact with the two-dimensional electron gas layer. The recess-structured conductive contact has at least one side surface defined to have a rounded wavy shape. | 09-18-2014 |
20150340434 | SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination. | 11-26-2015 |