Patent application number | Description | Published |
20110024886 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 02-03-2011 |
20120056261 | BI-DIRECTIONAL, REVERSE BLOCKING BATTERY SWITCH - Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package. | 03-08-2012 |
20120181676 | POWER SEMICONDUCTOR DEVICE PACKAGING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 07-19-2012 |
20120181677 | SEMICONDUCTOR DEVICE PACKAGE WITH TWO COMPONENT LEAD FRAME - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 07-19-2012 |
20130009296 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body. | 01-10-2013 |
20130009297 | SEMICONDUCTOR DEVICE PACKAGE HAVING CONFIGURABLE LEAD FRAME FINGERS - Embodiments of the present invention relate to the use of configurable lead frame fingers in a semiconductor device package. More specifically, the lead frame of a device package can include a plurality of fingers used to support and provide electrical contact to the die. The die can include a plurality of contacts that comprise a series of parallel columns located a certain distance from one another, and the fingers of the lead frame can be configured to align with the contacts. The lead frame can have multiple terminals, each with one or more fingers and pins. As such, each lead frame configuration may be utilized with different configurations of die. | 01-10-2013 |
20130017652 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE PACKAGE WITH A HEATSINK - Embodiments of the present invention relate to forming semiconductor device package with a heat sink. In one embodiment, a subassembly comprising a die attached to a lead frame is formed, a heat sink is provided in a molding cavity, and the subassembly is coupled to the heat sink while the heat sink is in the molding cavity. In certain embodiments, a second component of the lead frame can be substituted for the heat sink. Such techniques can simplify the manufacturing process for semiconductor packages having a heat sink or lead frame with a second component. | 01-17-2013 |
Patent application number | Description | Published |
20090005572 | METHODS FOR PREPARING DIAZONAMIDES - This invention relates to novel macrocyclic lactams intermediates useful for the preparation of diazonamide analogs. This invention also relates to a novel electrochemical oxidative cyclization for the preparation of such macrocyclic lactams, and their further elucidation to provide diazonamide analogs. | 01-01-2009 |
20090076076 | INHIBITORS OF CYSTEINE PROTEASES AND METHODS OF USE THEREOF - The present invention relates to semicarbazone or thiosemicarbazone inhibitors of cysteine proteases and methods of using such compounds to prevent and treat protozoan infections such as trypanosomiasis, malaria and leishmaniasis. The compounds also find use in inhibiting cysteine proteases associated with carcinogenesis, including cathepsins B and L. | 03-19-2009 |
20090163446 | DIAZONAMIDE ANALOGS WITH IMPROVED SOLUBILITY - Diazonamide A analogs, and the salts, esters and conjugates thereof, having improved aqueous solubility are provided. Also provided are pharmaceutical compositions, and methods for preparing and using such compounds and compositions for the treatment of proliferative diseases. | 06-25-2009 |
20100022607 | DIAZONAMIDE ANALOGS - Novel diazonamide analogs having anti-mitotic activity, useful for the treatment of cancer and other proliferative disorders are provided. | 01-28-2010 |
20100035946 | INDOLINE ANTI-CANCER AGENTS - Indoline compounds having anti-mitotic activity, useful for the treatment of cancer and other proliferative disorders are provided. | 02-11-2010 |
20110021784 | Methods for Preparing Diazonamides - This invention relates to novel macrocyclic lactams intermediates useful for the preparation of diazonamide analogs. This invention also relates to a novel electrochemical oxidative cyclization for the preparation of such macrocyclic lactams, and their further elucidation to provide diazonamide analogs. | 01-27-2011 |
20120065169 | OLIGONUCLEOTIDE ANALOGUES HAVING MODIFIED INTERSUBUNIT LINKAGES AND/OR TERMINAL GROUPS - Oligonucleotide analogues comprising modified intersubunit linkages and/or modified 3′ and/or 5′-end groups are provided. The disclosed compounds are useful for the treatment of diseases where inhibition of protein expression or correction of aberrant mRNA splice products produces beneficial therapeutic effects. | 03-15-2012 |
20120190862 | Methods for Preparing Diazonamides - This invention relates to novel macrocyclic lactams intermediates useful for the preparation of diazonamide analogs. This invention also relates to a novel electrochemical oxidative cyclization for the preparation of such macrocyclic lactams, and their further elucidation to provide diazonamide analogs. | 07-26-2012 |
20120264763 | Indoline Anti-Cancer Agents - Indoline compounds having anti-mitotic activity, useful for the treatment of cancer and other proliferative disorders are provided. | 10-18-2012 |
20140330006 | FUNCTIONALLY-MODIFIED OLIGONUCLEOTIDES AND SUBUNITS THEREOF - Functionally-modified oligonucleotide analogues comprising modified intersubunit linkages and/or modified 3′ and/or 5′-end groups are provided. The disclosed compounds are useful for the treatment of diseases where inhibition of protein expression or correction of aberrant mRNA splice products produces beneficial therapeutic effects. | 11-06-2014 |
20150073140 | OLIGONUCLEOTIDE ANALOGUES HAVING MODIFIED INTERSUBUNIT LINKAGES AND/OR TERMINAL GROUPS - Oligonucleotide analogues comprising modified intersubunit linkages and/or modified 3′ and/or 5′-end groups are provided. The disclosed compounds are useful for the treatment of diseases where inhibition of protein expression or correction of aberrant mRNA splice products produces beneficial therapeutic effects. | 03-12-2015 |
Patent application number | Description | Published |
20090250796 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 10-08-2009 |
20120264287 | METHOD FOR FORMING AN INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance. | 10-18-2012 |
20140167249 | INTERCONNECT STRUCTURE AND FABRICATION METHOD - An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate. | 06-19-2014 |
20140167283 | INTERCONNECT STRUCTURE AND FABRICATION METHOD - A carbon-containing dielectric layer can be formed on a substrate. A protective layer can be formed on the carbon-containing dielectric layer to prevent carbon loss from the carbon-containing dielectric layer by performing a surface treatment to the carbon-containing dielectric layer using a gas at least containing silicon and hydrogen. A hard mask layer can be formed on the protective layer. A through hole can be formed in the carbon-containing dielectric layer using the hard mask layer as a mask to expose a surface of the substrate for forming a contact plug in the through hole. | 06-19-2014 |
20140167285 | INTERCONNECT STRUCTURE AND FABRICATION METHOD - An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed in the substrate. At least two porous films can be formed over the substrate and can include a first porous film having a first pore size, and a second porous film having a second pore size formed on the first porous film. The first porous size and the second porous size are different. The interconnect can be formed through the plurality of porous films to provide electrical connection to the semiconductor device in the substrate. | 06-19-2014 |
20140191411 | INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating an interconnection structure. The method includes providing a substrate having certain semiconductor devices, a metal layer electrically connecting with the semiconductor devices, and a barrier layer on the metal layer. The method also includes forming a dielectric layer on the substrate; and forming an antireflective coating on the dielectric layer. Further, the method includes forming a second mask having a first pattern corresponding to a through hole in the dielectric layer, wherein the antireflective coating significantly reduces lithographic light reflection to avoid photoresist residue in the first pattern; and forming a through hole by etching the dielectric layer and the antireflective coating covering the dielectric layer using the second mask as an etching mask. Further, the method also includes forming a via by filling the through hole with a conductive material. | 07-10-2014 |
20140191412 | INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive layer on the semiconductor substrate, and forming a second conductive layer with smaller grain sizes by doping the first conductive layer. Further, the method includes forming an interconnection pad by patterning the second conductive layer, and forming a connection wire on the interconnection pad. | 07-10-2014 |
20140291817 | SEMICONDUCTOR DEVICE INCLUDING POROUS LOW-K DIELECTRIC LAYER AND FABRICATION METHOD - Semiconductor devices including porous low-k dielectric layers and fabrication methods are provided. A dielectric layer is formed on a substrate by introducing and polymerizing a main reaction gas on a surface of the substrate. The main reaction gas has a chemical structure including a ring-shaped group, silicon, carbon, and hydrogen, and the ring-shaped group includes at least carbon and hydrogen. A porous low-k dielectric layer is then formed from the dielectric layer by curing the dielectric layer with UV light. | 10-02-2014 |
20150028483 | NOVEL METHOD FOR ELECTROMIGRATION AND ADHESION USING TWO SELECTIVE DEPOSITION - A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination. | 01-29-2015 |
20150035152 | Interconnection structures for semiconductor devices and fabrication methods of forming interconnection structures for semiconductor devices utilizing to-be-etched layer made of porous low-K dielectric material and a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) - A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a to-be-etched layer made of porous low dielectric constant material on one surface of the semiconductor substrate. The method also includes forming a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) on the to-be-etched layer; and etching the first hard mask layer to have patterns corresponding to positions of subsequently formed openings. Further, the method includes forming the plurality of openings without substantial undercut between the to-be-etched layer and the first hard mask layer in the to-be-etched layer using the first hard mask layer as an etching mask; and forming a conductive structure in each of the openings. | 02-05-2015 |
20160049328 | METHOD FOR IMPROVING ADHESION BETWEEN POROUS LOW K DIELECTRIC AND BARRIER LAYER - A semiconductor device and method for manufacturing the same are provided. The method includes providing a semiconductor substrate, forming a porous low-k dielectric layer on the semiconductor substrate, forming a through-hole and a trench of a copper interconnect structure, performing a helium plasma treatment on an exposed surface of the porous low-k dielectric layer, performing a nitrogen plasma treatment on the exposed surface of the porous low-k dielectric layer to form a silicon nitride layer, performing an argon plasma treatment on the silicon nitride layer, and forming a diffusion barrier layer on bottoms and sidewalls of the through-hole and the trench of the copper interconnect structure. Through the successive helium, nitrogen and argon plasma treatments, the low-k dielectric layer has a smooth and dense surface that increases the adhesion strength between the low-k dielectric layer and the diffusion barrier layer to improve reliability and yield of the semiconductor device. | 02-18-2016 |
20160049365 | INTERCONNECT STRUCTURE - An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate. | 02-18-2016 |
20160064506 | SEMICONDUCTOR DEVICE HAVING METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF - The present disclosure provides a semiconductor device including a metal gate structure and formation method thereof. The semiconductor device includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a trench. A diffusion barrier layer is disposed over a bottom surface and sidewall surfaces of the trench in the dielectric layer. The diffusion barrier layer includes at least a titanium-nitride stacked layer. The titanium-nitride stacked layer includes a TiNx layer disposed over the bottom surface and the sidewall surfaces of the trench, a TiN layer on the TiNx layer, and a TiNy layer on the TiN layer, x<1 and y>1. A metal gate is filled in the trench and disposed on the diffusion barrier layer. | 03-03-2016 |
Patent application number | Description | Published |
20090062414 | System and method for producing damping polyurethane CMP pads - A solid product formed by polymerizing a urethane prepolymer in the presence of a curative has a Bashore rebound that is less than about 38%. Preferably, the urethane prepolymer is an aliphatic isocyanate polyether prepolymer and the curative includes an aromatic diamine and a triol. To form a microcellular polyurethane material, the urethane prepolymer is frothed with inert gas, in the presence of a surfactant, then cured. The polyurethane can by employed to form highly damping CMP pads that have low rebound and can dissipate irregular energy and stabilize polishing to yield improved uniformity and less dishing. | 03-05-2009 |
20090137120 | DAMPING POLYURETHANE CMP PADS WITH MICROFILLERS - A system for preparing a microcellular polyurethane material, includes a froth, prepared, for instance, by inert gas frothing a urethane prepolymer, preferably an aliphatic isocyanate polyether prepolymer, in the presence of a surfactant; a filler soluble in a CMP slurry; and a curative, preferably including an aromatic diamine and a triol. To produce the microcellular material, the froth can be combined with the filler, e.g., PVP, followed by curing the resulting mixture. The microcellular material has a low rebound and can dissipate irregular energy and stabilize polishing to yield improved uniformity and less dishing. CMP pads using the microcellular material have pores created by inert gas frothing throughout the pad polymer body and additional surface pores created by dissolution of fillers during polishing, providing flexibility in surface softness and pad stiffness. | 05-28-2009 |
20120015519 | DAMPING POLYURETHANE CMP PADS WITH MICROFILLERS - A system for preparing a microcellular polyurethane material, includes a froth, prepared, for instance, by inert gas frothing a urethane prepolymer, preferably an aliphatic isocyanate polyether prepolymer, in the presence of a surfactant; a filler soluble in a CMP slurry; and a curative, preferably including an aromatic diamine and a triol. To produce the microcellular material, the froth can be combined with the filler, e.g., PVP, followed by curing the resulting mixture. The microcellular material has a low rebound and can dissipate irregular energy and stabilize polishing to yield improved uniformity and less dishing. CMP pads using the microcellular material have pores created by inert gas frothing throughout the pad polymer body and additional surface pores created by dissolution of fillers during polishing, providing flexibility in surface softness and pad stiffness. | 01-19-2012 |
Patent application number | Description | Published |
20110195043 | Dimeric Smac Mimetics - The invention provides small molecule mimics of the Smac peptide that are dimers or dimer-like compounds having two binding domains connected by a linker These compounds are useful to promote apoptosis. The invention includes pharmaceutical compositions comprising such compounds and methods to use them to treat conditions including cancer and autoimmune disorders. | 08-11-2011 |
20120196907 | Diazonamide Analogs - Novel diazonamide analogs having anti-mitotic activity, useful for the treatment of cancer and other proliferative disorders are provided. | 08-02-2012 |
20120270841 | Diazonamide Analogs - Diazonamide analogs having anti-mitotic activity, useful for the treatment of cancer and other proliferative disorders, and related pharmaceutical compositions are provided. | 10-25-2012 |
20130344026 | Dimeric Smac Mimetics - The invention provides small molecule mimics of the Smac peptide that are dimers or dimer-like compounds having two binding domains connected by a linker. These compounds are useful to promote apoptosis. The invention includes pharmaceutical compositions comprising such compounds and methods to use them to treat conditions including cancer and autoimmune disorders. | 12-26-2013 |
20140100193 | Diazonamide Analogs - Diazonamide analogs having anti-mitotic activity, useful for the treatment of cancer and other proliferative disorders, and related pharmaceutical compositions are provided. | 04-10-2014 |