Patent application number | Description | Published |
20120079293 | UPGRADE KIT AND POWER MANAGEMENT DEVICE FOR AN UPGRADE KIT - A power management device for an upgrade kit for upgrading a target system to a digital system is provided. The power management device includes a sensor configured to sense a power status of the target system, and a power distribution unit configured to power on or off all subsystems of the upgrade kit according to the power status. | 03-29-2012 |
20120140543 | One Time Programming Memory and Method of Storage and Manufacture of the Same - The present invention relates to a one time programming memory and method of storage and manufacture of the same. It belongs to microelectronic memory technology and manufacture field. The one time programming memory comprises a diode ( | 06-07-2012 |
20120161094 | 3D SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density. | 06-28-2012 |
20120235112 | RESISTIVE SWITCHING MEMORY AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to the microelectronics field, and particularly, to a resistive switching memory and a method for manufacturing the same. The memory may comprise a lower electrode, a resistive switching layer, and an upper electrode. The resistive switching layer may have carbon nano-tubes embedded therein. Growth of a conductive filament in the resistive switching layer can be facilitated and controlled under an externally applied bias by a local electric field enhancement effect of the carbon nano-tubes, so as to improve performances and stability of the device. The resistive switching memory according to the present disclosure can have a good resistive switching capability. Further, the operating voltage and the resistance value of the device can be well controlled by controlling the length and position of the carbon nano-tubes in the resistive switching layer. | 09-20-2012 |
20120248503 | SEMICONDUCTOR MEMORY CELL, DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect. | 10-04-2012 |
20120275220 | THREE-DIMENSIONAL MULTI-BIT NON-VOLATILE MEMORY AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to the field of microelectronics manufacture and memories. A three-dimensional multi-bit non-volatile memory and a method for manufacturing the same are disclosed. The memory comprises a plurality of memory cells constituting a memory array. The memory array may comprise: a gate stack structure; periodically and alternately arranged gate stack regions and channel region spaces; gate dielectric layers for discrete charge storage; periodically arranged channel regions; source doping regions and drain doping regions symmetrically arranged to each other; bit lines led from the source doping regions and the drain doping regions; and word lines led from the gate stack regions. The gate dielectric layers for discrete charge storage can provide physical storage spots to achieve single-bit or multi-bit operations, so as to achieve a high storage density. According to the present disclosure, the localized charge storage characteristic of the charge trapping layer and characteristics such as a longer effective channel length and a higher density of a vertical memory structure are utilized, to provide multiple storage spots in a single memory cell. Therefore, the storage density is improved while good performances such as high speed are ensured. | 11-01-2012 |
20120281452 | RESISTIVE RANDOM MEMORY CELL AND MEMORY - The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell. The present disclosure uses the asymmetric tunneling barrier layer for rectifying, so as to enable selection of the resistive random memory cell. The method for manufacturing the asymmetric tunneling barrier layer does not involve doping or high-temperature annealing processes, and the thickness of the asymmetric tunneling barrier layer is relatively small, which helps 3D high-density integration of the resistive random memory. | 11-08-2012 |
20120305883 | METAL OXIDE RESISTIVE SWITCHING MEMORY AND METHOD FOR MANUFACTURING SAME - The present disclosure relates to the microelectronics field, and particularly, to a metal oxide resistive switching memory and a method for manufacturing the same. The method may comprise: forming a W-plug lower electrode above a MOS device; sequentially forming a cap layer, a first dielectric layer, and an etching block layer on the W-plug lower electrode; etching the etching block layer, the first dielectric layer, and the cap layer to form a groove for a first level of metal wiring; sequentially forming a metal oxide layer, an upper electrode layer, and a composite layer of a diffusion block layer/a seed copper layer/a plated copper layer in the groove for the first level of metal wiring; patterning the upper electrode layer and the composite layer by CMP, to form a memory cell and the first level of metal wiring in the groove in the first dielectric layer; and performing subsequent processes to complete the metal oxide resistive switching memory. According to the present disclosure, the manufacture process can be simplified, without incorporating additional exposure steps in the standard process, resulting in advantages such as reduced cost. | 12-06-2012 |
20130044299 | PROJECTION-TYPE PHOTOLITHOGRAPHY SYSTEM USING COMPOSITE PHOTON SIEVE - The present disclosure relates to the field of micro-nano fabrication, and provides a projection-type photolithography system using a composite photon sieve. The system comprises: a lighting system, a mask plate, a composite photon sieve and a substrate, which are arranged in order. The lighting system is adapted to generate incident light and irradiate the mask plate with the incident light. The mask plate is adapted to provide an object to be imaged by the composite photon sieve, and the incident light reaches the composite photon sieve after passing through the mask plate. The composite photon sieve is adapted to perform imaging, by which a pattern on the mask plate is imaged on the substrate. The substrate is adapted to receive an image of the pattern on the mask plate imaged by the composite photon sieve. According to the present disclosure, because the composite photon sieve is used instead of a projection objective lens in a conventional projection-type photolithography system, the advantage of high efficiency in the conventional projection-type photolithography system can be reserved, and also photolithography can be performed in batches rapidly, so that photolithography efficiency can be improved. Meanwhile, costs can be effectively cut down and the system can be reduced in size. | 02-21-2013 |
20130119341 | RESISTIVE RANDOM ACCESS MEMORY CELL AND MEMORY - A Resistive Random Access Memory (RRAM) cell and a memory are disclosed. In one embodiment, the RRAM cell comprises a two-state resistor and a resistive switching memory cell connected in series. The two-state resistor can supply relatively large currents under both positive and negative voltage polarities. As a result, it is possible to reduce leakage paths in a crossbar array of memory cells, and thus to suppress reading crosstalk. | 05-16-2013 |
20130203227 | METHOD FOR MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - The present disclosure provides a method for manufacturing a three-dimensional semiconductor memory device. In the method, a storage array is divided into a plurality of storage sub-arrays. As a result, a respective via of each storage sub-array can be etched respectively, which is different from the prior art, where a via for a bottom electrode of a plurality of layers of resistive cells is etched at one time. The vias are filled with metal so that storage sub-arrays are connected with each other. The method for manufacturing the three-dimensional semiconductor memory device according to the present disclosure can substantially reduce process complexity and difficulty of etching process in high-density integration, and also improve a number of layers of the resistive cells integrated in the storage array. | 08-08-2013 |
20140177039 | SUB-WAVELENGTH EXTREME ULTRAVIOLET METAL TRANSMISSION GRATING AND MANUFACTURING METHOD THEREOF - A method of manufacturing a sub-wavelength extreme ultraviolet metal transmission grating is disclosed. In one aspect, the method comprises forming a silicon nitride self-supporting film window on a back surface of a silicon-based substrate having both surfaces polished, then spin-coating a silicon nitride film on a front surface of the substrate with an electron beam resist HSQ. Then, performing electron beam direct writing exposure on the HSQ, developing and fixing to form a plurality of grating line patterns and a ring pattern surrounding the grating line patterns. Then depositing a chrome material on the front surface of the substrate through magnetron sputtering. Then, removing the chrome material inside the ring pattern. Then, growing a gold material on the front surface of the substrate through atomic layer deposition. Lastly, removing the gold material on the chrome material outside the ring pattern as well as on and between the grating line patterns, thereby only retaining the gold material on sidewalls of the grating line patterns. | 06-26-2014 |