Patent application number | Description | Published |
20110006416 | STRUCTURE AND METHOD FOR FORMING PILLAR BUMP STRUCTURE HAVING SIDEWALL PROTECTION - A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer. | 01-13-2011 |
20110227216 | Under-Bump Metallization Structure for Semiconductor Devices - An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer. | 09-22-2011 |
20110241202 | Dummy Metal Design for Packaging Structures - An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad. | 10-06-2011 |
20120178252 | Dummy Metal Design for Packaging Structures - A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern. | 07-12-2012 |
20130026623 | Semiconductor Devices, Packaging Methods and Structures - Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region. | 01-31-2013 |
20130093079 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 04-18-2013 |
20140070403 | Packaging Methods and Packaged Devices - Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die. | 03-13-2014 |
20140091471 | Apparatus and Method for a Component Package - A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. | 04-03-2014 |
20140097532 | Thermally Enhanced Package-on-Package (PoP) - A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip. | 04-10-2014 |
20140103540 | Cooling Channels in 3DIC Stacks - An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through. | 04-17-2014 |
20140117532 | Bump Interconnection Ratio for Robust CPI Window - The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump interconnection structure allows for optimized packaging assembly yield and bond integrity. | 05-01-2014 |
20140159203 | Substrate Pad Structure - A structure comprises a first pad protruding over a top surface of a package substrate, wherein the first pad is of a first elongated shape, a second pad embedded in the package substrate, wherein the second pad is of a second elongated shape and a via coupled between the first pad and the second pad. | 06-12-2014 |
20140191391 | ELONGATED BUMP STRUCTURES IN PACKAGE STRUCTURE - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2. | 07-10-2014 |
20140231987 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 08-21-2014 |
20150069595 | Apparatus and Method for a Component Package - A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. | 03-12-2015 |
20150303160 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 10-22-2015 |
20150318188 | Substrate Pad Structure - A structure comprises a plurality of top pads protruding over a top surface of a package substrate, wherein a top pad comprises a first half-circle portion, a second half-circle portion and a first rectangular portion between the first half-circle portion and the second half-circle portion, a plurality of bottom pads embedded in the package substrate, wherein a bottom pad comprises a third half-circle portion, a fourth half-circle portion and a second rectangular portion between the third half-circle portion and the fourth half-circle portion and a plurality of vias coupled between the top pads and their respective bottom pads. | 11-05-2015 |
20160027752 | Elongated Bump Structures in Package Structure - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d | 01-28-2016 |
Patent application number | Description | Published |
20080285363 | Self-feedback control pipeline architecture for memory read path applications - A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory. | 11-20-2008 |
20080304331 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application - The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem. | 12-11-2008 |
20080304332 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application - The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem. | 12-11-2008 |
20090175101 | Self-feedback control pipeline architecture for memory read path applications - A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory. | 07-09-2009 |
Patent application number | Description | Published |
20120007677 | Class AB Operational Amplifier and Output Stage Quiescent Current Control Method - A class AB operational amplifier includes: a first transistor, for generating a first current; a second transistor, where a second source voltage of the second transistor is equal to a first source voltage of the first transistor, for generating an output stage quiescent current; and an output stage quiescent current controller, coupled to a gate and a source of the first transistor, for controlling a first drain-to-source voltage of the first transistor to be equal to a second drain-to-source voltage of the second transistor. A ratio of the output stage quiescent current to the first current is equal to a ratio of a second W/L ratio of the second transistor to a first W/L ratio of the first transistor. | 01-12-2012 |
20120013400 | Current Control Circuit, Class AB Operational Amplifier System and Current Control Method - A current control circuit for controlling a bias current of a class AB operational amplifier includes: a low current source, for generating a low bias current; a high current source, for generating a high bias current, which is greater than the low bias current; and a comparing and selecting unit, coupled to an output terminal of the class AB operational amplifier, for selecting one of the low bias current and the high bias current to output as the bias current according to an output voltage of the class AB OP. | 01-19-2012 |
20120105121 | Device and Method for Signal Amplification - A signal amplification device for amplifying a signal according to a gain indication signal is disclosed. The signal amplification device includes a pulse width modulator for generating a pulse width modulation signal according to the gain indication signal, a counter for counting a period number of the pulse width modulation signal according to a standard clock signal, and an amplifier for amplifying the signal according to the period number. | 05-03-2012 |
20120105134 | Method and Device for Sharing Pin and Functional Device Using the Same - A pin sharing method for controlling a plurality of functions of a chip via a versatile pin of the chip is disclosed. The pin sharing method includes dividing a voltage range of the versatile pin into a plurality of sections according to the plurality of functions, and assigning the plurality of sections to correspond to a plurality of modes of the plurality of functions. | 05-03-2012 |
20120121109 | Analog-to-digital Converting Method and Functional Device Using the Same - An analog-to-digital converting method for converting an analog signal to a digital signal is disclosed. The analog-to-digital converting method includes decomposing the analog signal into a major analog signal and a minor analog signal, converting the major analog signal to a major digital signal, determining to which of a plurality of default sections the minor analog signal belongs to generate a minor digital signal correspondingly, and combining the major digital signal and the minor digital signal to form the digital signal. | 05-17-2012 |
20130169363 | Body Biasing Device and Operational Amplifier thereof - A body biasing device for an amplifier which has a P-type differential pair and outputs an output signal at an output node according to a differential input signal pair is disclosed. The body biasing device includes a detection unit coupled to the operational amplifier for detecting a detected voltage related to the differential input signals and accordingly outputting a control signal; and a selection unit coupled to the detection unit and the operational amplifier for outputting a body bias to the P-type differential pair according to the control signal. | 07-04-2013 |
20130241644 | Dynamic Power Control Method and Circuit thereof - The present invention discloses a dynamic power control method utilized in an amplifier. The dynamic power control method includes detecting an absolute difference between a positive supply voltage of the amplifier and an output voltage of the amplifier, to acquire a positive voltage difference; detecting an absolute difference between a negative supply voltage of the amplifier and the output voltage of the amplifier, to acquire a negative voltage difference; and adjusting the positive supply voltage and the negative supply voltage according to the positive voltage difference, the negative voltage difference and a threshold. | 09-19-2013 |
20140062592 | POP-FREE SINGLE-ENDED OUTPUT CLASS-D AMPLIFIER - A pop-free single-ended output class-D amplifier includes: an input signal generator for generating an input signal; a power supply for supplying input power; a reference voltage generator for generating a reference voltage; a gain-adjustable stage for generating an amplified signal according to the reference voltage and adjusting a gain of the single-ended output class-D amplifier; a pulse width modulation module for outputting a pulse width modulation signal according to the reference voltage, the amplified signal, and the input power; a low-pass filter for low-pass filtering the pulse width modulation signal to generate an output voltage; and a logic controller for generating at least one control signal to control the reference voltage generator, the gain-adjustable stage, and the pulse width modulation module according to the input power, the reference voltage, and the pulse width modulation signal. | 03-06-2014 |
20140294205 | OUTPUT-STAGE CIRCUIT AND METHOD FOR OVER CURRENT PROTECTION THEREOF AND AUDIO AMPLIFY SYSTEM - An output-stage circuit is disclosed. The output-stage circuit includes high-side output driver, first body selector, low-side output driver, second body selector and inductance. When output current is larger than current threshold value so as to make the low-side output driver generate overcurrent, the low-side output driver controlled by second control signal is disabled, and the high-side output driver controlled by first control signal is enabled so as to create first current channel. When output current is larger than current threshold value so as to make the high-side output driver generate overcurrent, the high-side output driver controlled by the first control signal is disabled, and the low-side output driver controlled by the second control signal is enabled so as to create second current channel to avoid current flowing through low-side output driver's body, and thus reduce the output current and voltage spiking of the output voltage. | 10-02-2014 |
Patent application number | Description | Published |
20080303572 | Spread Spectrum Device and Related Random Clock Generator for a Switching Amplifier - A random clock generator for a spread spectrum modulating device includes a random number generator for generating a plurality of random number signals according to a first square wave signal and a control signal, a reference wave generator coupled to the random number generator for generating a triangular signal and a second square wave signal according to the plurality of random number signals, and a trigger signal generator coupled to the random number generator and the reference wave generator, for generating the first square wave signal according to the second square wave signal. | 12-11-2008 |
20090160551 | Switching Amplifier - A switching amplifier includes an input end for receiving an input signal, a reference signal reception end for receiving a reference signal, a feedback end for receiving a feedback signal, an output end for outputting an output signal, an integration circuit for performing integration operation on the input signal according to the output signal and the feedback signal, so as to generate an integration result, a comparison circuit coupled to the integration circuit, the reference signal end, and the output end, for comparing the integration result and the reference signal, so as to generate the output signal for the output end, and a feedback circuit coupled between an output end of the integration circuit and the feedback end, for generating the feedback signal for the feedback end to clamp the integration result to a predetermined value when the integration result reaches the predetermined value. | 06-25-2009 |
20110074376 | Output Driving Circuit Capable of Reducing EMI Effect - An output driving circuit capable of reducing EMI effect includes a non-overlapping signal generation unit for generating a first non-overlapping signal and a second non-overlapping signal according to an input signal, a pre-driver for generating a first pre-driving signal and a second pre-driving signal according to the first non-overlapping signal and the second non-overlapping signal, a high-side switch, a low-side switch, and a control unit for controlling the high-side switch or the low-side switch to be switched into a weak on state to reduce load inductive current effect for a load. | 03-31-2011 |
20110074505 | Offset Voltage Calibration Method and Apparatus and Amplifier Thereof - An offset voltage calibration method is disclosed, which is utilized for calibrating an offset voltage of an electronic device during a calibration period. The offset voltage calibration method includes generating a control signal according to an output signal of the electronic device, counting a count value and generating an offset indication signal according to the control signal, stopping counting and generating a final count value according to a compensation value after the output signal changes state, generating a calibration signal according to the count value or the final count value, and calibrating the offset voltage according to the offset indication signal and the calibration signal. | 03-31-2011 |
Patent application number | Description | Published |
20110090713 | FLEXIBLE BACKLIGHT MODULE - A flexible backlight module includes a light source module and a flexible light guide panel, wherein the flexible light guide panel has a light incident surface, a light reflecting surface, and a light outgoing surface. The light incident surface of the flexible light guide panel is directly connected and thereby optically coupled to the light source module so that the light emitted by the light source module can be completely coupled to the flexible light guide panel. Consequently, the loss of light is reduced while the luminous efficiency of light is increased. Light entering the flexible light guide panel is reflected by the light reflecting surface to the light outgoing surface and then projected outward. The flexible light guide panel can be curved as needed thanks to its flexibility and thus features a wide application range. | 04-21-2011 |
20110121723 | LED Base Structure with Embedded Capacitor - An LED base structure with an embedded capacitor includes a body, at least one pair of metal layers, at least one dielectric layer, and at least two conductive channels. The body is an insulating base. The metal layers are disposed in the body, and the dielectric layer is disposed between the metal layers, so as to form an embedded capacitor. The conductive channels are electrically connected to the metal layers, respectively. The LED base structure is further electrically connected to a resistor for forming a resistor-capacitor delay circuit whereby a phase delay is effectuated whenever AC power is supplied to the LED base structure, so as to control the time for switching on one of two parallel-connected LEDs and, as a result, prevent the LEDs from flashing which might otherwise arise when the LEDs are supplied with AC power. | 05-26-2011 |
20120018773 | ALTERNATING-CURRENT LIGHT EMITTING DIODE STRUCTURE WITH OVERLOAD PROTECTION - The present invention relates to an alternating current (AC) light emitting diode (LED) structure with overload protection, which comprises an AC LED, a heat dissipating unit and an overload protecting unit. The AC LED is thermally connected with the heat dissipating unit, and the overload protecting unit is connected in series between the AC LED and a power source. Thus, when an overload current is inputted to the AC LED structure, the temperature of the overload protecting unit will rise to disconnect the AC LED from the power source. In this way, an open-circuit status can be produced timely in the AC LED structure to block the power input into the AC LED for purpose of protection against overload. | 01-26-2012 |
20130126914 | HIGH-VOLTAGE AC LIGHT-EMITTING DIODE STRUCTURE - A high-voltage alternating current (AC) light-emitting diode (LED) structure is provided. The high-voltage AC LED structure includes a circuit substrate and a plurality of high-voltage LED (HV LED) chips. Each one of the HV LED chips includes a first substrate, an adhering layer, first ohmic contact layers, epi-layers, a first insulating layer, at least two first electrically conducting plates, at least two second electrically conducting plates, and a second substrate. The HV LED chips manufactured by a wafer-level process are coupled to the low-cost circuit substrate to produce the downsized high-voltage AC LED structure. | 05-23-2013 |
20130127352 | HIGH-VOLTAGE AC LED STRUCTURE - The present invention provides a high-voltage alternating current light-emitting diode (AC LED) structure. The high-voltage AC LED structure includes a circuit substrate and a plurality of AC LED chips. The AC LED chips each include an insulated substrate, an LED set, a first metal layer and a second metal layer. The AC LED chips manufactured by a wafer level process are coupled to the low-cost circuit substrate to produce the downsized high-voltage AC LED structure. | 05-23-2013 |
Patent application number | Description | Published |
20110044035 | PARALLEL BRIDGE CIRCUIT STRUCTURE AND HIGH-VOLTAGE PARALLEL BRIDGE CIRCUIT STRUCTURE - A parallel bridge circuit structure and a high-voltage parallel bridge circuit structure are disclosed. The parallel bridge circuit structure includes a first bridge circuit and a second bridge circuit. The first bridge circuit includes a plurality of first diodes, and the second bridge circuit includes a plurality of second diodes. Each of the second diodes is exclusively connected to one of the first diodes in parallel. With the design of the parallel connection between the first bridge circuit and the second bridge circuit, break of the entire circuit caused by a damaged diode is prevented. Moreover, with the aid of the AC signal phase delay circuit structure, the output voltage of the parallel bridge circuit structure can be stable and continuous voltage, while the high-voltage parallel bridge circuit structure includes a plurality of parallel bridge circuit structures so as to endure a high voltage input. | 02-24-2011 |
20110165715 | MANUFACTURING METHOD FOR AN AXIALLY SYMMETRIC LIGHT-EMITTING DIODE ASSEMBLY - A manufacturing method for an axially symmetric light-emitting diode assembly disclosed herein includes steps of: providing a substrate; and forming a plurality of light-emitting areas on the substrate. The substrate has a central axis. The light-emitting areas are arranged with axial symmetry around the central axis while being insulated from each other. Each of the light-emitting areas has at least one light-emitting diode, and the light-emitting diodes are electrically connected to each other. Since the light-emitting areas are formed on the substrate with the axially symmetric arrangement, the axially symmetric light-emitting diode assembly can present a well symmetric light pattern. | 07-07-2011 |
20130095585 | MULTI-FIELD ARRANGING METHOD OF LED CHIPS UNDER SINGLE LENS - A multi-field arranging method of LED chips under a single lens includes the steps of: setting a first concentric circle on a bottom of a hemispherical lens, wherein the first concentric circle is centered at an axis of the hemispherical lens; equidistantly arranging plural first LED chips on the first concentric circle; setting a second concentric circle, which is also centered at the same axis as the first concentric circle, and the second concentric circle is larger than the first concentric circle in radius; and equidistantly arranging plural second LED chips and plural third LED chips on the second concentric circle. The present invention allows the LED chips to present symmetrical light patterns through the hemispherical lens, thereby obtaining a light field with evener color mixture and evener color temperature distribution in every illuminating direction. | 04-18-2013 |
20130109001 | HIGH-LUMINANCE UV LED NAIL LAMP STRUCTURE AND LED LIGHT SOURCE MODULE THEREOF | 05-02-2013 |
20130134447 | LOW-LIGHT-EMITTING-ANGLE HIGH-LUMINANCE UV LED NAIL LAMP STRUCTURE AND LED LIGHT SOURCE MODULE THEREOF - A low-light-emitting-angle high-luminance ultraviolet (UV) light-emitting diode (LED) nail lamp structure and an LED light source module thereof are provided. The UV LED nail lamp structure includes a housing and an LED light source module. The LED light source module is provided in the housing and has a plurality of UV LEDs, wherein the light-emitting angle of each UV LED ranges between 25° and 80°. The UV LED nail lamp structure features high luminance and enhanced lighting effect. | 05-30-2013 |
20140077710 | LED LAMP STRUCTURE DRIVEN BY DOUBLE CURRENT AND DOUBLE CURRENT DRIVING METHOD THEREOF - Disclosed are an LED lamp structure driven by double current and a double current driving method thereof. The LED lamp structure driven by double current includes a COB package, a temperature sensor, and a controller. The COB package is provided therein with a blue LED chipset to be driven by a first current and a red LED chipset to be driven by a second current. The temperature sensor detects the working temperature of the red LED chipset, and the controller performs dynamic adjustment on the second current according to the working temperature so as to stabilize the color temperature of the LED lamp structure. Thus, as soon as the LED lamp structure is activated, its color temperature will be stabilized to ensure user comfort, which may otherwise be disturbed by variation of the color temperature. | 03-20-2014 |
20140091330 | LED PACKAGE STRUCTURE WITH TRANSPARENT ELECTRODES - The present invention discloses a LED package structure with transparent electrodes. The electrode layers | 04-03-2014 |
20140145221 | LED LAMP STRUCTURE WITH HEAT SINK - An LED lamp structure with a heat sink includes a reflection cup, an LED module, and a cover, in addition to the heat sink. The reflection cup has an inside bottom surface, a reflection surface, an outside bottom surface, and a light exit. The LED module is thermally conductively and fixedly provided on the inside bottom surface. The cover covers the LED module. The heat sink is thermally conductively connected to the outside bottom surface. The LED lamp structure is efficient in not only light extraction but also heat dissipation. | 05-29-2014 |
20140183444 | HIGH-VOLTAGE FLIP-CHIP LED STRUCTURE AND MANUFACTURING METHOD THEREOF - A high-voltage flip-chip LED structure and a manufacturing method thereof are disclosed. The manufacturing method includes: providing a die substrate, depositing a first passivation layer, forming a co-electrical-connecting layer, depositing a second passivation layer, depositing a mirror layer, forming two conductive tunnels by etching, and providing two connecting metal layers. The die substrate includes a sapphire substrate and multiple LED chips thereon. The fully transparent co-electrical-connecting layer, formed after formation of the first passivation layer, electrically connects the LED chips in series. The outer surface of the deposited second passivation layer is a flat passivation surface that enables the mirror layer thereon to be level and reflect light without optical path difference. The two connecting metal layers are provided for electrical conduction. The high-voltage flip-chip LED structure thus formed has fully transparent electrodes and can output light without optical path difference. | 07-03-2014 |
Patent application number | Description | Published |
20140139373 | MULTIPATH SWITCHING SYSTEM HAVING ADJUSTABLE PHASE SHIFT ARRAY - A multipath switching system comprising of an adjustable phase shift array includes, an adjustable phase shift array module and a control module. The adjustable phase shift array module receives a radio-frequency (RF) signal, and includes at least one RF switch, at least one coupler and at least one phase shifter. The at least one RF switch, the at least one coupler and the at least one phase shifter form a number of transmission paths. The transmission paths respectively produce the processed transmission RF signals corresponding to different phase shifts to an antenna array. The control module controls the at least one RF switch and the at least one phase shifter of the adjustable phase shift array module, so that the antenna array radiates a wireless signal whose direction is corresponding to a predetermined angle in space polar coordinates. | 05-22-2014 |
20140140705 | METHOD AND APPARATUS FOR INTERFERENCE SUPPRESSION IN RADIO-OVER-FIBER COMMUNICATION SYSTEMS - According to one embodiment of a method for interference suppression in radio-over-fiber communication systems, the method uses a mode selection module to continuously update real time information of at least two mobile stations and determine to enter a cross mode or a single mode. In the single mode, when a mobile station approaches a switching point, a single mode command is issued to control at least one first specific remote antenna unit (RAU). In the cross mode, when an immediate cross condition is a new cross condition, a new cross mode table is generated, and when the position of any one mobile station of the at least two mobile stations cross a threshold, a cross mode command is issued to control at least one second specific RAU according to a corresponding cross mode table. | 05-22-2014 |
20140157297 | Marketing Method and Computer System thereof for Cloud System - A marketing method for combining a plurality of marketing information and a cloud system including a display device, a network server and a mobile device is disclosed. The marketing method includes obtaining a recognition information corresponding to at least a marketing information to process a video information to be a processed video information, installing an application software in the mobile device, displaying the processed video information on the display device, utilizing the application software and a detection module of the mobile device to obtain the recognition information while displaying the processed video information, and utilizing the network server to obtain a search result corresponding to the marketing information according to the recognition information. | 06-05-2014 |
Patent application number | Description | Published |
20130334921 | MOTOR STRUCTURE - A motor structure includes a case, a rotor, a first magnet, a second magnet and at least one magnetic conductive plate, wherein the rotor is disposed within an accommodating slot of the case, and the first magnet is disposed between the case and the rotor. The first magnet comprises a first end portion spaced apart with the case to define a first separation space. The second magnet comprises a second end portion spaced apart with the case to define a second separation space. A spacing slot is composed of the first separation space and the second separation space, and the at least one magnetic conductive plate is disposed within the spacing slot. The magnetic conduction through the at least one magnetic conductive plate enables to lower the reluctance of the motor structure for prevention of magnetic flux leakage therefore increasing the air-gap flux density. | 12-19-2013 |
20140334677 | MULTI-COMPUTER VISION RECOGNITION SYSTEM FOR LEVEL CROSSING OBSTACLE - A multi-computer vision recognition system for a level crossing obstacle is disclosed, comprising vision image systems, a position determination system, an obstacle determination resolution system and a power unit, where vision image systems which may operate all day long operate simultaneously, information of the single vision image systems is each computed by using the position determination system, and then the computed result is introduced to the obstacle determination resolution system for determination, whereby achieving an increased obstacle recognition result and a promoted obstacle recognition accuracy. | 11-13-2014 |
20150162788 | ROTOR CORE ASSEMBLY FOR A RELUCTANCE MOTOR AND MANUFACTURING METHOD OF THE SAME - A rotor core assembly for a reluctance motor and a manufacturing method of the same, wherein the rotor core assembly has multiple silicon steel laminations and a nonmagnetic material. The silicon steel laminations are axially stacked, and each silicon steel lamination has multiple magnetic flux sections. Each magnetic flux section has multiple arcuate grooves and multiple salient poles. The arcuate grooves are concentrically arranged. The salient poles protrude into the grooves. The nonmagnetic material is disposed in the grooves, and is wrapped around the salient poles, which enables the silicon steel laminations to remain securely assembled together. The salient poles are disposed in the grooves to avoid ruining the magnetic line of force. As a result, the rotor core assembly can keep rigidity of the assembled silicon steel laminations, and can keep the integrity of the magnetic circuit. | 06-11-2015 |
Patent application number | Description | Published |
20120236727 | NETWORK INTERFACE TEST DEVICE - A network interface test device for testing a plurality of network interfaces of a network apparatus includes a control unit, a first port, a switch unit, and a plurality of second ports. The control unit generates a control signal required for programming a router line in the switch unit. The programmed router line provides a path for switching a signal between the first port and the second ports. A parallel or cross network test can be performed on a test packet signal of an external network test interface at gigabit Ethernet transmission speed for example, using the switching path. Hence, the network interface test device enables a network test to be performed on a plurality of network interfaces by a network test interface. | 09-20-2012 |
20120269068 | TESTING SYSTEM - A testing system for testing a network apparatus has a plurality of network ports. The system includes a signal generating device for providing a test packet to the network apparatus; a network apparatus connecting device for connecting to the network apparatus; a switching device for switching between a plurality of router lines; and a controlling device for controlling a test procedure, by controlling selection and cycling of the router lines to perform a test on the network ports one by one and allowing the network ports to return the test packet by the test packet return instruction. Accordingly, the network connection status of the network ports of the network apparatus is determined according to the test packet. The test system allows a test to be conducted on the network ports of the network apparatus quickly and at low costs. | 10-25-2012 |
20130015890 | METHOD AND SYSTEM FOR CALIBRATING FREQUENCYAANM CHOU; MING-HUNGAACI TAIPEI CITYAACO TWAAGP CHOU; MING-HUNG TAIPEI CITY TWAANM HSIEH; CHING-FENGAACI TAIPEI CITYAACO TWAAGP HSIEH; CHING-FENG TAIPEI CITY TW - A method for calibrating frequency, applicable to calibrating a frequency signal generated by a frequency generating unit of an apparatus at a preset frequency, includes obtaining the cycle number of the clock rate of a frequency signal based on a reference signal and a clock mask synchronous with the frequency signal; obtaining a frequency of the frequency signal based on the cycle number; correcting the frequency according to a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the frequency of the frequency signal by increasing the quantity of the phase shift signals, so as to calibrate the frequency signal generated by the frequency generating unit. | 01-17-2013 |
20130018615 | METHOD AND SYSTEM FOR MEASURING FREQUENCYAANM CHOU; MING-HUNGAACI TAIPEI CITYAACO TWAAGP CHOU; MING-HUNG TAIPEI CITY TWAANM WANG; NAI-JIANAACI TAIPEI CITYAACO TWAAGP WANG; NAI-JIAN TAIPEI CITY TWAANM HSIEH; CHING-FENGAACI TAIPEI CITYAACO TWAAGP HSIEH; CHING-FENG TAIPEI CITY TW - A method for measuring frequency includes the steps of obtaining the cycle number of the clock rate of a signal under test based on a reference signal and a clock mask synchronous with the signal under test; obtaining a frequency of the signal under test based on the cycle number; correcting the frequency of the signal under test based on a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the frequency of the signal under test by increasing the quantity of the phase shift signals. The method enhances the accuracy of the obtained frequency of the signal under test, speeds up frequency measurement, and reduces the required circuit areas. A system for measuring frequency is further introduced for use with the method. | 01-17-2013 |
20130018616 | FREQUENCY COUNTERAANM CHOU; MING-HUNGAACI TAIPEI CITYAACO TWAAGP CHOU; MING-HUNG TAIPEI CITY TWAANM WANG; NAI-JIANAACI TAIPEI CITYAACO TWAAGP WANG; NAI-JIAN TAIPEI CITY TWAANM HSIEH; CHING-FENGAACI TAIPEI CITYAACO TWAAGP HSIEH; CHING-FENG TAIPEI CITY TW - A frequency counter obtains a cycle number of a clock of a target signal by a reference signal and a clock mask synchronous with the target signal, calculates a frequency of the target signal based on the cycle number, corrects the frequency according to a plurality of phase shift signals generated based on the reference signal, and minimizes an error of the calculated frequency by increasing the quantity of the phase shift signals, so as to enhance the accuracy of the calculated frequency of the target signal, speed up measurement, and reduce required circuit areas. | 01-17-2013 |
20130018627 | METHOD AND SYSTEM FOR MEASURING SPEEDAANM CHOU; MING-HUNGAACI TAIPEI CITYAACO TWAAGP CHOU; MING-HUNG TAIPEI CITY TWAANM HSIEH; CHING-FENGAACI TAIPEI CITYAACO TWAAGP HSIEH; CHING-FENG TAIPEI CITY TW - A method for measuring speed involves calculating and measuring speed of an object based on a distance and a time obtained by a method for measuring distance and a method for measuring time, respectively. The time between distance measuring sessions is obtained using the cycle number of a reference signal based on a clock mask synchronous with the distance measuring sessions. The time is corrected according to a plurality of phase shift signals generated based on the reference signal. An error of the time is minimized by increasing the quantity of the phase shift signals. The method enhances the accuracy of the measured time between distance measuring sessions, speeds up speed measurement, and reduces the required circuit areas. A system for measuring speed is further introduced for use with the method. | 01-17-2013 |
20130018630 | METHOD AND SYSTEM FOR MEASURING DISTANCEAANM CHOU; MING-HUNGAACI TAIPEI CITYAACO TWAAGP CHOU; MING-HUNG TAIPEI CITY TWAANM HSIEH; CHING-FENGAACI TAIPEI CITYAACO TWAAGP HSIEH; CHING-FENG TAIPEI CITY TW - A method for measuring distance involves calculating a distance based on light speed and a time taken by an optical signal to travel to an object and return therefrom. The method includes calculating a time based on a cycle number of a reference signal under a clock mask synchronized with emission and reception of the optical signal; correcting the time according to a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the time by increasing the quantity of the phase shift signals. The method enhances the accuracy of the measured time taken by an optical signal to travel to an object and return therefrom, speeds up measurement, and reduces the required circuit areas. A system for measuring distance is further introduced for use with the method. | 01-17-2013 |
20130018631 | METHOD AND SYSTEM FOR MEASURING TIMEAANM CHOU; MING-HUNGAACI TAIPEI CITYAACO TWAAGP CHOU; MING-HUNG TAIPEI CITY TWAANM HSIEH; CHING-FENGAACI TAIPEI CITYAACO TWAAGP HSIEH; CHING-FENG TAIPEI CITY TW - A method for measuring time includes setting a clock mask by a starting signal and an ending signal generated upon commencement of measurement and termination of measurement, respectively; obtaining a cycle number of a reference signal under the clock mask to calculate a preliminary time; correcting the preliminary time according to a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the preliminary time by increasing the quantity of the phase shift signals. The method enhances the accuracy of the measured time, times up time measurement, and reduces the required circuit areas. A system for measuring time is further introduced for use with the method. | 01-17-2013 |
Patent application number | Description | Published |
20080196699 | Gravity-controlled constant-pressure and pressure-regulation device - A gravity-controlled constant-pressure and pressure-regulation device includes a canister, a weight block, and a seal head. The canister includes a metal layer, an epoxy resin layer, and a plastic sheet layer. The metal layer serves as an inner lining. The epoxy resin layer surrounds an outer circumference of the metal layer. The plastic sheet layer surrounds an outer circumference of the epoxy resin layer. The weight block is movably received in the canister. The metal layer has an inner surface movably and receivingly engages the seal head. The weight block is mounted to the seal head. The weight block is movable upward and downward inside the canister by being acted upon by a gravity force of weight thereof and a lifting force induced by an internal pressure inside the canister to effect mass storage of air inside the canister and stable supply air at constant pressure. | 08-21-2008 |
20080197632 | Air-blower tidal power generation device - An air-blower tidal power generation device includes a rack, an air-blower mechanism, and a power generation mechanism. The air-blower mechanism includes a pumping device, a buoy, and an air conduit. The pumping device includes a cylinder and a stationary barrel movably coupled together. The power generation mechanism includes a constant-pressure and pressure-regulation device and a power generator having an air-driven turbine. Thus, tides move the buoy up and down to drive the pumping device for cyclically drawing and pumping air, and the air is preserved in the constant-pressure and pressure-regulation device to provide a constant pressure for subsequent and stable supply of airflow to the turbine for driving the power generator to generate power. | 08-21-2008 |
20090169121 | STATIC IMAGE COMPRESSION METHOD AND COMPUTER READABLE DATA STRUCTURE AND COMPUTER READABLE STORAGE MEDIUM - A static image compression method, a computer readable data structure, and a computer readable storage medium are described. Firstly, an image is segmented into a plurality of sub-images. Then, each sub-image is sequentially compressed into a sub-data frame having a start character, so as to generate a compressed data with the sub-data frames interconnected according to a sequence of the sub-images. Finally, the addresses of the start characters are recorded to generate an index data. Thereby, the start character of a particular block can be obtained from the index data, and the sub-image of the particular block is preferentially decoded and displayed. | 07-02-2009 |
20140118928 | ELECTRONIC DEVICE - An electronic device comprises a case, a heat source and a radiator. The heat source is disposed inside the case. The radiator is disposed on the case and the radiator is kept away from the heat source at a distance. The radiator comprises a case body. A plurality of cellular compartments formed by a plurality of partition plates is disposed inside the case body. The cellular compartments are filled with a heat dissipation material. The radiator absorbs the heat of the heat source through thermal radiation. | 05-01-2014 |
20140118942 | ELECTRONIC DEVICE - An electronic device includes a housing, a heat source located in the housing, and a heat dissipation device disposed in the housing. The heat dissipation device thermally contacts the heat source. The heat dissipation device includes a casing. A heat dissipation material is disposed in the casing. The heat dissipation material includes 15 to 30 percent volume of multiple copper materials, 50 to 85 percent volume of a phase change material and 15 to 20 percent volume of air. The heat dissipation device has a surface thermally contacting the heat source. A central area and an outer ring area are defined on the surface. The outer ring area surrounds the central area. A geometric midpoint of the central area overlaps that of the surface. The heat source is located in the outer ring area. The heat dissipation device absorbs heat from the heat source through thermal conduction. | 05-01-2014 |
20140118943 | ELECTRONIC DEVICE - An electronic device includes a housing, a heat source in the housing, and a heat dissipation device in the housing and separated from the heat source by a distance. The heat dissipation device includes a casing. A heat dissipation material is disposed in the casing. The heat dissipation material includes 15 to 30 percent volume of multiple copper materials, 50 to 85 percent volume of a phase change material, and 15 to 20 percent volume of air. The heat dissipation device has a surface facing the heat source. A central area and an outer ring area are defined on the surface. The outer ring area surrounds the central area. A geometric midpoint of the central area overlaps that of the surface. An orthographic projection region on the surface is in the outer ring area. The heat dissipation device absorbs heat from the heat source through thermal radiation. | 05-01-2014 |
20140118945 | ELECTRONIC DEVICE - An electronic device includes a housing, a heat source located in a casing, and a heat dissipation device disposed in a casing. The heat dissipation device is kept apart from the heat source. The heat dissipation device includes a casing having a heat dissipation material including 15 to 30 percent volume of multiple copper materials, 50 to 85 percent volume of a phase change material, and 15 to 20 percent volume of air. The casing has a surface facing the heat source. A central area and an outer ring area are defined on the surface. A geometric midpoint of the central area overlaps a geometric midpoint of the surface. An orthographic projection region of the heat source to the surface is located in the central area. The heat dissipation device absorbs heat generated by the heat source through thermal radiation. | 05-01-2014 |
20140118948 | ELECTRONIC DEVICE - An electronic device includes a housing, a heat source located inside a casing, and a heat dissipation device disposed inside a casing. The heat dissipation device is in thermal contact with the heat source. The heat dissipation device includes a casing having a heat dissipation material. The heat dissipation material includes 15 to 30 volume percent of multiple copper materials, 50 to 85 volume percent of a phase change material, and 15 to 20 volume percent of air. The casing has a surface being in thermal contact with the heat source. A central area and an outer ring area are defined on the surface. The outer ring area surrounds the central area. A geometric midpoint of the central area and a geometric midpoint of the surface are overlapped. The heat dissipation device absorbs heat generated by the heat source located in the central area through thermal conduction. | 05-01-2014 |
Patent application number | Description | Published |
20130092418 | CHIP-ON-FILM PANEL STRUCTURE - The present invention relates to a chip-on-film panel structure, which has a panel body and fan-out leads, first metal sheets, array leads and second metal leads thereon. The array leads are disposed at two sides of the fan-out leads, the second metal sheets are disposed at two sides of the first metal sheets, and the length of each of the second metal sheet is less than the length of each of the first metal sheet to form a lead-out area that the array leads are led out from the second metal sheets via the lead-out area. The chip-on-film panel structure having an arranged fan-out area for array leads can settle the problem of being difficult to narrow the frame of the panel because the array leads occupy available room for fan-out leads and force the fan-out area to expand longitudinally. | 04-18-2013 |
20130153905 | Flat Display Panel and Method for Forming the Same - The present invention proposes to a flat display panel and a method for forming the same. The flat display panel includes a plurality of rows of scan lines, a plurality of columns of data lines and a plurality of blocking lines which are parallel and overlapped to the data lines. The plurality of blocking lines are placed at one side of pixel electrodes one on one and made of the same metallic layer with the plurality of scan lines. Each blocking line made of the same metallic layer with the scan line is wider than a corresponding data line, so that light not blocked by the data line is blocked by the wider blocking line. | 06-20-2013 |
20130286331 | Liquid Crystal Display Module and Liquid Crystal Display Device - The present invention discloses a liquid crystal display device and liquid crystal display module thereof. The liquid crystal display module includes a color filter substrate, a thin film transistor substrate and seal. The thin film transistor substrate and the color film substrate are disposed oppositely, and the seal is disposed between the thin film transistor substrate and the color film substrate. The color filter substrate comprises a first glass substrate and black matrix. The seal comprises a first end part contacting the color filter substrate. No black matrix is disposed between the first end part and the color filter substrate, and the first end part is disposed as a shade structure. The liquid crystal display module and liquid crystal display device of the present invention provide the advantages of convenience for seal curing, facilitating narrow border design, and avoiding aggravating drive signal delay. | 10-31-2013 |
20140063426 | Liquid Crystal Display Panel and Manufacturing Method Thereof - The present invention provides a liquid crystal display panel, which comprises: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer; the first insulating layer being disposed on the first conductive layer and comprising at least two first via-holes corresponding respectively to at least two first subsidiary conductive regions so that at least two first subsidiary conductive regions being partially exposed through first via-holes; the second conductive layer being disposed on the first insulating layer; the second insulating layer being disposed on the second conductive layer; the second insulating layer being disposed on the second conductive layer and comprising at least two second via-holes corresponding respectively to at least two second subsidiary; a third conductive layer being connected with first subsidiary conductive regions and a second conductive layer. | 03-06-2014 |
20140063431 | Display Panel and Liquid Crystal Device with the Same - A display panel and a liquid crystal device are disclosed. The display panel includes a first substrate, a second substrate opposite to the first substrate, a sealant. The first substrate is arranged with a first alignment film. The second substrate is arranged with a second alignment film. The sealant surrounds the first substrate and the second substrate. A first wall is arranged on the first substrate, and the first wall is between an edge of the first alignment film and the sealant. A second wall is arranged on the second substrate, and the second wall is between an edge of the second alignment film and the plastic film. In this way, the distance between an active area and edges of the display panel is reduced so that the narrow bezel design may be implemented. | 03-06-2014 |
20140167160 | TFT array substrate - The present invention discloses a thin film transistor (TFT) array substrate, which includes a plurality of scan lines, data lines, and common electrode lines disposed on a substrate. The scan lines and the data lines cross with each other to define a plurality of pixel regions that have a plurality of TFTs disposed in the crossing regions therebetween. A plurality of pixel electrodes are disposed in the pixel regions. The TFT array substrate further includes a patterned shielding layer which is insulatively disposed below the data lines. The patterned shielding layer of the present invention can shield the back light directly, and the area of the black matrix on the color filter substrate can be reduced so as to increase the aperture ratio. | 06-19-2014 |
20150022211 | DETECTION CIRCUIT FOR DISPLAY PANEL - The present disclosure provides a detection circuit for a display panel, comprising: a shorting bar, with connection lines for introducing a test signal or a control signal arranged thereon; a transistor array, the gates of which are connected to the connection lines for introducing the control signal, wherein the connection lines for introducing the test signal are connected with the data lines or the scanning lines of the display panel via the sources and the drains of transistors, under the control signal, and a component, arranged between the gates of the transistor array and the shorting bar, for further reducing or increasing a voltage or current of the gates so that the transistor array can be cut off reliably when the control signal is a signal enabling the transistor array to be cut off. The detection circuit can further reduce the channel length of the thus being advantageous for the design of the narrow frame. | 01-22-2015 |
20150022749 | ARRAY SUBSTRATE AND DISPLAY PANEL - An array substrate and a display panel are disclosed. The array substrate includes at least one data line, at least one scanning line, and a pixel cell defined by the data line and the scanning line. The pixel cell includes an ITO thin film and at least one metallic layer below the ITO thin film. The ITO thin film electrically connects to the metallic layer via a through hole. The ITO thin film includes a slit arranged between the ITO thin film and the through hole, and the slit is arranged to avoid the disclination lines so as to improve the display performance. | 01-22-2015 |
20150146130 | Liquid Crystal Display Panel and Manufacturing Method for the Same - The present invention discloses a liquid crystal display (LCD) panel which includes a thin film transistor array substrate, a color filter substrate, a liquid crystal layer and a frame. The color filter substrate includes a transparent substrate, a black matrix layer and a coloring layer. The frame is disposed at an outer side edge of the liquid crystal layer. The present invention further discloses a method for manufacturing the LCD panel. The present invention can block an UV light by the black matrix layer and the coloring layer, and an UV mask can be omitted. | 05-28-2015 |
20150160485 | METHOD FOR CURING SEALANT IN MANUFACTURING OF LIQUID CRYSTAL PANEL AND LIQUID CRYSTAL PANEL - The present disclosure proposes a method for curing a sealant in manufacturing of a liquid crystal panel. The liquid crystal panel includes an array substrate, a color filter substrate and a liquid crystal layer between the array substrate and the color filter substrate, a first film layer capable of blocking light is arranged on the side of the color filter substrate facing the liquid crystal layer, and a sealant is arranged between the array substrate and the color filter substrate outside the liquid crystal layer, and the method includes: step 1, removing a portion of the first film layer corresponding to the sealant; and step 2, applying UV from one side of the color filter substrate of the liquid crystal panel to irradiate the sealant, thus curing the sealant. The present disclosure also proposes a liquid crystal panel. | 06-11-2015 |
20150362809 | AN ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure discloses an array substrate, belongs to the technical field of display technology, and solves the technical problem of low aperture ratio of prior liquid crystal display device. The array substrate comprises a plurality of sub pixel units arranged in an array and a plurality of signal lines, wherein one signal line of two adjacent signal lines is arranged in a first side of corresponding sub pixel units, and the other signal line is arranged in a second side of corresponding sub pixel units, said first side and said second side being one of opposite sides of the sub pixel units respectively. The array substrate of the present disclosure can be used in liquid crystal television, liquid crystal display, mobile phone, tablet personal computer and other display devices. | 12-17-2015 |
20150372010 | Thin Film Transistor Array Substrate and Method for Manufacturing the Same - The present invention proposes a TFT array substrate includes: a substrate; scan lines on the substrate; data lines intercrossing with the scan lines; a first insulating layer between the scan lines and the data lines; a second insulating layer on the first insulating layer and covering the data lines; a common electrode layer on the second insulating layer, comprising first holes located above the data lines. The first holes uncover the second insulating layer. The present invention decreases parasitic capacitance between the common electrode layer and data lines and between the common electrode layer and scan lines by decreasing overlaping sections between a common electrode layer and the data lines and between the common electrode layer and the scan lines. Therefore load of the data lines and the scan lines decreases, charge efficiency of the pixels increases, and display effect of an LCD panel is therefore improved. | 12-24-2015 |
Patent application number | Description | Published |
20100327284 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes. | 12-30-2010 |
20110128214 | DISPLAY PANEL - A display panel includes an array substrate, an opposite substrate and a display medium layer. A plurality of ring-like common lines of the array substrate are respectively located between two adjacent scan lines, and a plurality of date lines intersect with the scan lines and the ring-like common lines. Each pixel unit of the array substrate includes an active device, a pixel electrode and a connecting line. Each of the connecting line intersects with one of the scan lines and is electrically connected to the two adjacent ring-like common lines so as to connect the ring-like common lines to form a meshed common line. A transparent region is defined by a black matrix layer of the opposite substrate and the ring-like common lines. The black matrix layer does not cover the ring-like common lines at the corner of the transparent region near the connecting lines. | 06-02-2011 |
20120299004 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes. | 11-29-2012 |
Patent application number | Description | Published |
20140119905 | FAN STRUCTURE - A fan structure includes a casing, a fan, and two elastic members. The casing has an accommodation space. The fan is located in the accommodation space. The fan has a first side and a second side opposite to each other. One of the two elastic members is sandwiched between the casing and the first side of the fan. The other one of the two elastic members is sandwiched between the casing and the second side of the fan. The two elastic members normally keep the fan away from the casing, so as to make the fan contact the casing through the two elastic members, thereby achieving a damping effect. | 05-01-2014 |
20140126136 | MEMORY COMBINATION AND COMPUTER SYSTEM USING THE SAME - A memory combination includes a first riser board, a second riser board, and a pivotal plate. The first riser hoard includes a plurality of first memory sockets of which long axis directions are parallel to each other. The second riser board includes a plurality of second memory sockets of which long axis directions are parallel to each other. Two end of the pivotal plate are pivotally connected to the first riser board and the second riser board based on an axial direction respectively. When the first and second riser boards rotate to be perpendicular to the pivotal plate, the first memory sockets face the second riser board, and the second memory sockets face the first riser board. The axial direction is perpendicular to the long axis directions of the first memory sockets and the long axis directions of the second memory sockets. | 05-08-2014 |
20140133085 | MEMORY COMBINATION AND COMPUTER SYSTEM USING THE SAME - A memory combination is applied in a computer system. The computer system includes a motherboard. The motherboard includes a first riser slot and a second riser slot disposed side by side. The memory combination includes a first riser board and a second riser board. The first riser board is plugged into the first riser slot and includes a plurality of first memory sockets. The second riser board is plugged into the second riser slot and includes a plurality of second memory sockets. The first memory sockets face the second riser board, and the second memory sockets face the first riser board. The first memory sockets are unaligned with the second memory sockets. | 05-15-2014 |
20140139994 | MEMORY EXPANSION ASSEMBLY - A memory expansion assembly includes a first plate having first electrical slots and a first electrically connecting portion, a second plate pivotally connected to the first plate and having second electrical slots and a second electrically connecting portion, a first engaging assembly, and a second engaging assembly. The first electrical slots are electrically connected to the first electrically connecting portion. The second electrical slots are electrically connected to the second electrically connecting portion. The second plate is adapted to pivot relative to the first plate to have a folded position when the two are close to each other and an unfolded position when the two are away from each other. The first engaging assembly is disposed on a side of the first plate. The second engaging assembly is disposed on a side of the second plate. The first engaging assembly is removably engaged with the second engaging assembly. | 05-22-2014 |
20140140816 | FAN MODULE - A fan module includes a casing, a fan, and two vibration absorption assemblies. The casing has an accommodating space. The fan is located in the accommodating space and keeps a distance from the casing. Each of the two vibration absorption assemblies includes two first vibration absorption components and a second vibration absorption component. The two first vibration absorption components are respectively in contact with the fan and separated from the casing, respectively. The second vibration absorption component is connected with two first vibration absorption components and the casing, respectively. The first vibration absorption components and the second vibration absorption components are adapted for absorbing the vibration waves having different frequency ranges. | 05-22-2014 |