Patent application number | Description | Published |
20090317214 | NOVEL WAFER'S AMBIANCE CONTROL - A semiconductor manufacturing system, an interface system, a carrier, and a method for providing an ambient controlled environment is disclosed. The semiconductor manufacturing system comprises a plurality of process chambers; at least one interface system, wherein the interface system includes a first ambient control element; at least one carrier, wherein the carrier comprises a second ambient control element; and a control module coupled to the plurality of process chambers, the at least one interface system, and the at least one carrier. | 12-24-2009 |
20100015894 | CMP by Controlling Polish Temperature - A method for manufacturing integrated circuits on a wafer includes providing a facility-supplied room temperature solution; controlling the temperature of the facility-supplied room temperature solution to a desired temperature set point to generate a rinse solution; and rinsing a polishing pad using the rinse solution. The wafer is then polished by means of a chemical mechanical polishing process. | 01-21-2010 |
20100018029 | Rinsing Wafers Using Composition-Tunable Rinse Water in Chemical Mechanical Polish - An apparatus for manufacturing integrated circuits on a wafer includes a polish pad; a rinse arm movable over the polish pad; and a post-polish cleaner. The post-polish cleaner includes a brush for brushing the wafer; and a nozzle aiming at the wafer. The apparatus further includes a mixer configured to mix an additive and di-ionized water; and a pipe connecting the mixer to at least one of the rinse arm and the nozzle. | 01-28-2010 |
20110062580 | PROTECTION LAYER FOR PREVENTING UBM LAYER FROM CHEMICAL ATTACK AND OXIDATION - A protection layer formed of a CuGe | 03-17-2011 |
20110092064 | Preventing UBM Oxidation in Bump Formation Processes - A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer. | 04-21-2011 |
20110101527 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS - The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper. | 05-05-2011 |
20110278716 | METHOD OF FABRICATING BUMP STRUCTURE - A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer. | 11-17-2011 |
20110287628 | Activation Treatments in Plating Processes - A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature. | 11-24-2011 |
20120007228 | CONDUCTIVE PILLAR FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive pillar on a semiconductor die. A substrate is provided. A bond pad is over the substrate. A conductive pillar is over the bond pad. The conductive pillar has a top surface, edge sidewalls and a height. A cap layer is over the top surface of the conductive pillar. The cap layer extends along the edge sidewalls of the conductive pillar for a length. A solder material is over a top surface of the cap layer. | 01-12-2012 |
20120018878 | Doping Minor Elements into Metal Bumps - A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump. | 01-26-2012 |
20120286423 | Doping Minor Elements into Metal Bumps - A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump. | 11-15-2012 |
20130113094 | POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure. | 05-09-2013 |
20130127059 | Adjusting Sizes of Connectors of Package Components - A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component. | 05-23-2013 |
20130175685 | UBM Formation for Integrated Circuits - A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad. | 07-11-2013 |
20130187277 | CRACK STOPPER ON UNDER-BUMP METALLIZATION LAYER - A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings. | 07-25-2013 |
20130328190 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need. | 12-12-2013 |
20130334692 | Bonding Package components Through Plating - A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector. | 12-19-2013 |
20130341786 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. In one embodiment, a PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal pillars are coupled to the first packaged die. The metal pillars have a first portion proximate the first packaged die and a second portion disposed over the first portion. Each of the metal pillars is coupled to a solder joint proximate the second packaged die. | 12-26-2013 |
20140015122 | Method of Forming Post Passivation Interconnects - A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric layer on the passivation layer, applying a first patterning process to the first dielectric layer to form a first opening, forming a first seed layer over the first opening, filling the first opening with a conductive material, depositing a second dielectric layer on the first dielectric layer, applying a second patterning process to the second dielectric layer to form a second opening, forming an under bump metallization structure over the second opening and mounting an interconnect bump over the under bump metallization structure. | 01-16-2014 |
20140183746 | Zero Stand-Off Bonding System and Method - A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a first substrate and breaching the seal with a conductive member of a second substrate in order to bond the first substrate to the second substrate. | 07-03-2014 |
20140252594 | Package Structures and Methods for Forming the Same - A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed. | 09-11-2014 |
20140308764 | Adjusting Sizes of Connectors of Package Components - A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component. | 10-16-2014 |
Patent application number | Description | Published |
20120268551 | Image Interaction Device, Interactive Image Operating System, and Interactive Image Operating Method thereof - Before a large amount of information or messages is to be transmitted between image interaction devices, the information or messages are encoded into digital images to generate corresponding digital encoded images. When the digital encoded images are transmitted between the image interaction devices, the information or messages are transmitted along with the digital encoded images without introducing additional data transmission; and as a result, delay between the image interaction devices can be avoided, and real-time operations between the image interaction devices can be achieved. | 10-25-2012 |
20130215112 | Stereoscopic Image Processor, Stereoscopic Image Interaction System, and Stereoscopic Image Displaying Method thereof - A 3D face model is generated by calculating depths on a left image and a right image. An eye-distance of a user is determined according to the 3D face model. A precise stereoscopic digital image of the user is generated by integrating the 3D face model, the eye-distance, and a user digital image processed by human-body rendering and face morphing. The stereoscopic digital image generated by following the user's appearance can be utilized by the user to serve as an avatar, for enhancing entertainments of the user when the user plays an interactive game using the avatar with other players on the Internet. | 08-22-2013 |
20130329947 | IMAGE CAPTURING METHOD FOR IMAGE RECOGNITION AND SYSTEM THEREOF - An image capturing method includes providing at least three image capturing devices arranged along a same direction and an image processor, the at least three image capturing devices capturing at least three first images, determining a target object in the at least three first images, activating a first pair of image capturing devices of the at least three image capturing devices according to shooting angles of the target object in the at least three first images in order to capture a first pair of motion images, and the image processor performing image recognition to the target object of the first pair of motion images. | 12-12-2013 |