Patent application number | Description | Published |
20080253189 | MEMORY UNIT - A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The memory unit not only has the advantage of high speed operation of a static random access memory, but also functions as a non-volatile memory for saving data. | 10-16-2008 |
20080266960 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF AND CIRCUIT SYSTEM INCLUDING THE NON-VOLATILE MEMORY - A non-volatile memory including a memory cell is described. The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping layer. The first and the second charge trapping layer are respectively disposed on both sides of the first gate. The semiconductor layer is disposed on the first unit. The second unit is disposed on the semiconductor layer and is in mirror symmetry to the first unit. The second unit includes a second gate and a third and a fourth charge trapping layer respectively disposed on both sides of the second gate. The doped region is disposed at both sides of the semiconductor layer and serves as a common source/drain region of both the first and the second unit. | 10-30-2008 |
20080266969 | METHOD OF OPERATING NON-VOLATILE MEMORY - A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region. | 10-30-2008 |
20080316810 | MEMORY UNIT - A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has an advantage of high speed operation of a static random access memory (SRAM), but also has a function for storing data of a non-volatile memory. | 12-25-2008 |
20090185428 | OPERATING METHOD OF MULTI-LEVEL MEMORY CELL - An operating method of a memory cell is described, wherein the memory cell has a plurality of threshold voltages. The operating method includes programming the cell from an initial state to a programmed state. The initial state is an erased state having a threshold voltage between the lowest threshold voltage and the highest one among the plurality of threshold voltages. | 07-23-2009 |
20090186212 | NON-VOLATILE MEMORY AND METHODS FOR FABRICATING THE SAME - A non-volatile memory including a substrate, source/drain regions, a first insulating layer, a charge storage layer, a second insulating layer, and a conductive layer is provided. The source/drain regions are respectively disposed in the substrate apart from each other. The first insulating layer is disposed on the substrate between the source/drain regions. The charge storage layer is disposed on the first insulating layer. The second insulating layer is disposed on the charge storage layer, and a thickness of a peripheral region of the second insulating layer is greater than a thickness of an internal region of the second insulating layer. The conductive layer is disposed on the second insulating layer. | 07-23-2009 |
20090207656 | OPERATING METHOD OF MEMORY - An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state. | 08-20-2009 |
20090207658 | OPERATING METHOD OF MEMORY DEVICE - An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array | 08-20-2009 |
20090219763 | NON-VOLATILE MEMORY - A non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each cell including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate. A circuit provides a first voltage to the substrate and a second voltage to both S/D regions of each cell, wherein the difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes. The circuit also provides a voltage to the control gate and the period of applying the voltages are controlled such that the threshold voltages of all the cells converge in a tolerable range. | 09-03-2009 |
20100055890 | METHOD FOR FABRICATING NON-VOLATILE MEMORY - A method for fabricating a non-volatile memory is provided. The method includes a stacked structure and a consuming layer are formed in sequence over a substrate. A converting process is performed at a peripheral region of the consuming layer to form a first insulating layer. A conductive layer is formed over the stacked layer and the first insulating layer. | 03-04-2010 |
20100176436 | MEMORY DEVICES - A memory device is provided. The memory device includes a first control gate, a second control gate, a plurality of first charge storage elements, a plurality of second charge storage elements and a semiconductor. The plurality of first charge storage elements is beside the first control gate, and each of the first charge storage elements is located on the different side of the first control gate. The plurality of second charge storage elements is beside the second control gate. The semiconductor is located between the first and second control gates. | 07-15-2010 |