Patent application number | Description | Published |
20080203915 | MATERIAL OF PROTECTIVE LAYER, METHOD OF PREPARING THE SAME, PROTECTIVE LAYER FORMED OF THE MATERIAL, AND PLASMA DISPLAY PANEL INCLUDING THE PROTECTIVE LAYER - A material for preparing a protective layer for a PDP, which reduces discharge delay time, improves temperature dependency, and has enhanced ion strength; a method of preparing the same; a protective layer formed of the material; and a PDP including the protective layer. More particularly, a material for a protective layer that includes monocrystalline magnesium oxide doped with a rare earth element at an amount of 2.0×10−5−1.0×10−2 parts by weight per 1 part by weight of magnesium oxide (MgO), a method of preparing the monocrystalline magnesium oxide by crystallizing it at about 2,800° C., a protective layer formed of the same, and PDP including the protective layer. | 08-28-2008 |
20080317944 | Protecting layer, composite for forming the same, method of forming the protecting layer, plasma display panel comprising the protecting layer - A protecting layer is formed of a magnesium oxide and at least one additional component selected from the group consisting of a copper component selected from copper and a copper oxide, a nickel component selected from nickel and a nickel oxide, a cobalt component selected from cobalt and a cobalt oxide, and an iron component selected from iron and an iron oxide; a composite for forming the protecting layer; a method of forming the protecting layer; and a plasma display panel including the protecting layer. The protecting layer, which is used in a PDP, protects an electrode and a dielectric layer from a plasma ion generated by a gaseous mixture of Ne and Xe, or He, Ne, and Xe, and discharge delay time and dependency of the discharge delay time on temperature can be decreased and sputtering resistance can be increased. | 12-25-2008 |
20090058297 | PROTECTING LAYER COMPRISING MAGNESIUM OXIDE LAYER AND ELECTRON EMISSION PROMOTING MATERIAL, METHOD FOR PREPARING THE SAME AND PLASMA DISPLAY PANEL COMPRISING THE SAME - A protecting layer is formed of a magnesium oxide layer and electron emission promoting material formed on the magnesium oxide layer. The electron emission promoting material may be patterned on the magnesium oxide layer, or may be sprayed and heat-treated on the surface of the magnesium oxide layer. The protecting layer exhibits excellent electron emission characteristics while not being substantially damaged by plasma ions, thereby improving the reliability of a PDP. | 03-05-2009 |
20090153019 | Protecting layer having magnesium oxide particles at its surface, method of preparing the same, and plasma display panel comprising the protecting layer - Provided are a protecting layer for a plasma display panel (PDP), a method of forming the same, and a PDP including the protecting layer. The protecting layer includes a magnesium oxide-containing layer having a surface to which magnesium oxide-containing particles having a magnesium vacancy-impurity center (VIC) are attached. The protecting layer is resistant to plasma ions and has excellent electron emission effects, and thus, a PDP including the protecting layer can be operated at low voltage with high discharge efficiency. | 06-18-2009 |
20090167177 | Protective layer and plasma display panel including the same - A protective layer of a plasma display panel includes smoky magnesium oxide, the smoky magnesium oxide having single crystal magnesium oxide with a plurality of cavities therein. | 07-02-2009 |
20100141139 | Protective layer for plasma display panel, method of preparing the protective layer, and plasma display panel including the protective layer - A protective layer for a PDP, includes a doping source layer containing at least one dopant, and a body layer which contacts the doping source layer and includes at least one dopant diffused from the doping source layer. The protective layer is capable of reducing dopant loss and avoiding trade-offs/conflicts between a donor dopant and an acceptor dopant. | 06-10-2010 |
Patent application number | Description | Published |
20090004797 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a plurality of pillars which are arranged on a substrate in a first direction and a second direction that intersects the first direction, thereby forming a resulting structure, forming a capping layer on the resulting structure including the pillars, removing the capping layer formed on the substrate between the pillars to expose the substrate between the pillars, thereby forming a resulting structure, forming a metal layer on the resulting structure, forming a silicide layer on the exposed substrate between the pillars by applying a first heat treatment to the metal layer, removing a non-reacted silicide layer, and forming an isolation trench in the substrate which is between rows of the pillars arranged in the first direction and is under the silicide layer to define bit lines which surround the pillars and are extended to the first direction. | 01-01-2009 |
20090004813 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR - A method and system are provided for fabricating a semiconductor device that includes a vertical channel transistor. An area of a buried bit line is uniformly formed by an isolation trench. The width of the isolation trench is adjusted by controlling the thickness of spacers. Consequently, the area of the buried bit line is relatively large compared with that of a typical buried bit line. The resistance characteristics of the buried bit line are improved and stability and reliability of the semiconductor device are ensured. | 01-01-2009 |
20090004855 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns, etching the gate spacer layer at a bottom of the recess, and forming a plug on the recess, thereby forming a second resulting structure including the plug. | 01-01-2009 |
20090004861 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL - A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulation layer over the resultant structure, planarizing the hard mask pattern and the insulation layer until the pillars are exposed, and forming a storage electrode over the exposed pillars. | 01-01-2009 |