Patent application number | Description | Published |
20100214811 | CODING TECHNIQUES FOR IMPROVING THE SENSE MARGIN IN CONTENT ADDRESSABLE MEMORIES - A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word. | 08-26-2010 |
20100214829 | MEMORY PROGRAMMING - Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range. | 08-26-2010 |
20100214830 | MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION - Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell. | 08-26-2010 |
20100218071 | WRITING A SPECIAL SYMBOL TO A MEMORY TO INDICATE THE ABSENCE OF A DATA SIGNAL - A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol. | 08-26-2010 |
20110096594 | MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION - Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell. | 04-28-2011 |
20110228600 | MEMORY PROGRAMMING - Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range. | 09-22-2011 |
20110246703 | CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES - Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword. | 10-06-2011 |
20110252215 | COMPUTER MEMORY WITH DYNAMIC CELL DENSITY - A computer memory with dynamic cell density including a method that obtains a target size for a first memory region. The first memory region includes first memory units operating at a first density. The first memory units are includes in a memory in a memory system. The memory is operable at the first density and a second density. The method also includes: determining that a current size of the first memory region is not within a threshold of the target size and that the first memory region is smaller than the target size; identifying a second memory unit currently operating at the second density in a second memory region, the second memory unit included in the memory; and dynamically reassigning, during normal system operation, the second memory unit into the first memory region, the second memory unit operating at the first density after being reassigned to the first memory region. | 10-13-2011 |
20110317481 | PLANAR PHASE-CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS - A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film. | 12-29-2011 |
20110320881 | ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM - Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link. | 12-29-2011 |
20120096328 | MULTI-WRITE ENDURANCE AND ERROR CONTROL CODING OF NON-VOLATILE MEMORIES - Multi-write endurance and error control coding of non-volatile memories including a method for receiving write data and a write address of a memory page in a memory. The write data is partitioned into a plurality of sub-blocks, each sub-block including q bits of the write data. Error correction bits are generated at the computer in response to the sub-blocks and to an error correction code (ECC). At least one additional sub-block containing the error correction bits are appended to the partitioned write data and a write word is generated. The write word is generated by performing for each of the sub-blocks: selecting a codeword such that the codeword encodes the sub-block and is consistent with current electrical charge levels of the plurality of memory cells associated with the memory page; concatenating the selected codewords to form the write word; and writing the write word to the memory page. | 04-19-2012 |
20120127790 | ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES - Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory. | 05-24-2012 |
20120131304 | Adaptive Wear Leveling via Monitoring the Properties of Memory Reference Stream - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses. | 05-24-2012 |
20120144249 | Program Disturb Error Logging and Correction for Flash Memory - Program disturb error logging and correction for a flash memory including a computer implemented method for storing data. The method includes receiving a write request that includes data and a write address of a target page in a memory. A previously programmed page at a specified offset from the target page is read from the memory. Contents of the previously programmed page are compared to an expected value of the previously programmed page. Error data is stored in an error log in response to contents of the previously programmed page being different than the expected value of the previously programmed page, the error data describing an error in the previously programmed page and the error data used by a next read operation to the previously programmed page to correct the error in the previously programmed page. The received data is written to the target page in the memory. | 06-07-2012 |
20120144272 | PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY - Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output. | 06-07-2012 |
20120218814 | WRITE BANDWIDTH IN A MEMORY CHARACTERIZED BY A VARIABLE WRITE TIME - A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays. | 08-30-2012 |
20120226962 | WEAR-FOCUSING OF NON-VOLATILE MEMORIES FOR IMPROVED ENDURANCE - Storing data in memory using wear-focusing techniques for improved endurance. A method for storing the data includes receiving write data to be written into a memory that is logically divided into a plurality of regions. The plurality of regions includes a first region and a second region that are implemented by the same memory technology. The memory is subject to degradation as a result of write operations. The write data is classified as dynamic data or static data. The write data is encoded using a first type of encoding in response to the write data being classified as dynamic. The write data encoded using the first type of encoding is stored in the first region of the memory. The write data is encoded using a second type of encoding and stored in the second region of the memory in response to classifying the write data as static data. | 09-06-2012 |
20120226963 | BAD BLOCK MANAGEMENT FOR FLASH MEMORY - Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory. | 09-06-2012 |
20120311262 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state. | 12-06-2012 |
20130011993 | PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS - A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer. | 01-10-2013 |
20130013860 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting. | 01-10-2013 |
20130013886 | ADAPTIVE WEAR LEVELING VIA MONITORING THE PROPERTIES OF MEMORY REFERENCE STREAM - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses. | 01-10-2013 |
20130016556 | PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS - A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region. | 01-17-2013 |
20130166821 | LOW LATENCY AND PERSISTENT DATA STORAGE - Persistent data storage with low latency is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed. | 06-27-2013 |
20130166822 | SOLID-STATE STORAGE MANAGEMENT - Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The sold-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address. | 06-27-2013 |
20130166826 | SOLID-STATE DEVICE MANAGEMENT - An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address. | 06-27-2013 |
20130200321 | POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES - Defining an active region of a phase change memory (PCM) cell including depositing a first layer of material having a first chemical composition. A second layer of material having a second chemical composition is deposited on top of the first layer of material. An electrical current pulse is applied to locally heat a region of the first layer of material and the second layer of material to cause at least one of an inter-diffusion and a liquid mixing of the first layer of material and the second layer of material. This results in in the PCM cell containing a self-aligned region that includes a phase change material that is a mixture of the first chemical composition and the second chemical composition. | 08-08-2013 |
20130212427 | RECLAIMING DISCARDED SOLID STATE DEVICES - Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced. | 08-15-2013 |
20140006897 | CORRECTION OF STRUCTURED BURST ERRORS IN DATA | 01-02-2014 |
20140043927 | METHOD FOR OPTIMIZING REFRESH RATE FOR DRAM - A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set. | 02-13-2014 |
20140063997 | DRAM REFRESH - A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh. | 03-06-2014 |
20140136769 | SOLID-STATE STORAGE MANAGEMENT - Solid-state storage management for a system, the management including establishing, externally to a solid-state storage board, a correspondence between a first logical address and a first physical address on solid-state storage devices located on the solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses. The correspondence between the first logical address and the first physical address is accepted by the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in a location on a solid-state memory device that is accessible by an address translator module, the address translator module and the solid-state memory device located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address. | 05-15-2014 |
20140136770 | LOW LATENCY AND PERSISTENT DATA STORAGE - Persistent data storage with low latency is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed. | 05-15-2014 |
20140164692 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164820 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164871 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140164874 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140185397 | HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR - A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element. | 07-03-2014 |
20140185398 | HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR - A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element. | 07-03-2014 |
20140195765 | IMPLEMENTING USER MODE FOREIGN DEVICE ATTACHMENT TO MEMORY CHANNEL - A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software. | 07-10-2014 |
20140223117 | SECURING THE CONTENTS OF A MEMORY DRIVE - A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device. | 08-07-2014 |
20140223120 | SECURING THE CONTENTS OF A MEMORY DEVICE - A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device. | 08-07-2014 |
20140317219 | LOCAL DIRECT STORAGE CLASS MEMORY ACCESS - A queued, byte addressed system and method for accessing flash memory and other non-volatile storage class memory, and potentially other types of non-volatile memory (NVM) storage systems. In a host device, e.g., a standalone or networked computer, having attached NVM device storage integrated into a switching fabric wherein the NVM device appears as an industry standard OFED™ RDMA verbs provider. The verbs provider enables communicating with a ‘local storage peer’ using the existing OpenFabrics RDMA host functionality. User applications issue RDMA Read/Write directives to the ‘local peer (seen as a persistent storage) in NVM enabling NVM memory access at byte granularity. The queued, byte addressed system and method provides for Zero copy NVM access. The methods enables operations that establish application private Queue Pairs to provide asynchronous NVM memory access operations at byte level granularity. | 10-23-2014 |
20140317336 | LOCAL DIRECT STORAGE CLASS MEMORY ACCESS - A queued, byte addressed system and method for accessing flash memory and other non-volatile storage class memory, and potentially other types of non-volatile memory (NVM) storage systems. In a host device, e.g., a standalone or networked computer, having attached NVM device storage integrated into a switching fabric wherein the NVM device appears as an industry standard OFED™ RDMA verbs provider. The verbs provider enables communicating with a ‘local storage peer’ using the existing OpenFabrics RDMA host functionality. User applications issue RDMA Read/Write directives to the ‘local peer (seen as a persistent storage) in NVM enabling NVM memory access at byte granularity. The queued, byte addressed system and method provides for Zero copy NVM access. The methods enables operations that establish application private Queue Pairs to provide asynchronous NVM memory access operations at byte level granularity. | 10-23-2014 |
20140359197 | IMPLEMENTING REINFORCEMENT LEARNING BASED FLASH CONTROL - A method and system are provided for implementing enhanced flash storage control using reinforcement learning to provide enhanced performance metrics. A flash controller, such as a Reinforcement Learning (RL) flash controller, is coupled to a flash storage. The flash controller defines a feature set of flash parameters determined by a predefined one of a plurality of optimization metrics. The optimization metric is adapted dynamically based upon system workload and system state. The flash controller employing the feature set including at least one feature responsive to erase operations; computes a current system state responsive to the employed feature set; selects actions at each time step by sensing the computed current system state for performing an action to maximize a long term reward, and moves to another state in the system while obtaining a short-term reward for the performed action. | 12-04-2014 |
20140365480 | PERSONALIZED LOW LATENCY COMMUNICATION - Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation. | 12-11-2014 |
20140365503 | ESTIMATION OF CLOSENESS OF TOPICS BASED ON GRAPH ANALYTICS - Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment. | 12-11-2014 |
20140365504 | ESTIMATION OF CLOSENESS OF TOPICS BASED ON GRAPH ANALYTICS - Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment. | 12-11-2014 |
20140365584 | PERSONALIZED LOW LATENCY COMMUNICATION - Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation. | 12-11-2014 |