Patent application number | Description | Published |
20090289240 | NON-VOLATILE MULTI-BIT MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source. | 11-26-2009 |
20090289290 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 11-26-2009 |
20100006813 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed. | 01-14-2010 |
20100102406 | MAGNETIC STACK DESIGN - A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer. | 04-29-2010 |
20100197104 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 08-05-2010 |
20100309717 | NON-VOLATILE MULTI-BIT MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate. | 12-09-2010 |
20110180888 | MAGNETIC STACK DESIGN - A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer. | 07-28-2011 |
20110267873 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 11-03-2011 |
20120104348 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 05-03-2012 |
20130187115 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Programmable metallization memory cells include an electrochemically active electrode, an inert electrode and an internal layer between the electrochemically active electrode and the inert electrode. The internal layer having a fast ion conductor material and an apertured layer having a plurality of apertures defined by an electrically insulating material. Each aperture defines at least a portion of a column of fast ion conductor material having superionic clusters. | 07-25-2013 |