Patent application number | Description | Published |
20080198647 | METHOD AND APPARATUS FOR BITLINE AND CONTACT VIA INTEGRATION IN MAGNETIC RANDOM ACCESS MEMORY ARRAYS - In one embodiment, the invention is a method and apparatus for bitline and contact via integration in magnetic random access memory arrays. One embodiment of a magnetic random access memory according to the present invention includes a magnetic tunnel junction and a top wire that surrounds the magnetic tunnel junction on at least three sides. | 08-21-2008 |
20080211055 | Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit - Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization. | 09-04-2008 |
20080239784 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures. | 10-02-2008 |
20080239785 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure. | 10-02-2008 |
20080243972 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures. | 10-02-2008 |
20080308801 | STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION - A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter. | 12-18-2008 |
20090046493 | METHOD AND APPARATUS FOR FABRICATING SUB-LITHOGRAPHY DATA TRACKS FOR USE IN MAGNETIC SHIFT REGISTER MEMORY DEVICES - In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section. | 02-19-2009 |
20100276768 | SIDEWALL COATING FOR NON-UNIFORM SPIN MOMENTUM-TRANSFER MAGNETIC TUNNEL JUNCTION CURRENT FLOW - A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a different electrical conductivity than the low conductivity layer. The spacer material is etched from horizontal surfaces so that the spacer material remains only on sidewalls of the hard mask and a stud. A further etch process leaves behind the sidewall-spacer material as a conductive link between a free magnetic layer and the conductive hard mask, around the low-conductivity layer. A difference in electrical conductivity between the stud and the spacer material enhances current flow along the edges of the free layer within the MTJ stack and through the spacer material formed on the sidewalls. | 11-04-2010 |
20110049655 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 03-03-2011 |
20110204459 | SIDEWALL COATING FOR NON-UNIFORM SPIN MOMENTUM-TRANSFER MAGNETIC TUNNEL JUNCTION CURRENT FLOW - A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a different electrical conductivity than the low conductivity layer. The spacer material is etched from horizontal surfaces so that the spacer material remains only on sidewalls of the hard mask and a stud. A further etch process leaves behind the sidewall-spacer material as a conductive link between a free magnetic layer and the conductive hard mask, around the low-conductivity layer. A difference in electrical conductivity between the stud and the spacer material enhances current flow along the edges of the free layer within the MTJ stack and through the spacer material formed on the sidewalls. | 08-25-2011 |
20120299136 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 11-29-2012 |
20120326250 | SPIN TRANSFER TORQUE CELL FOR MAGNETIC RANDOM ACCESS MEMORY - Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via. | 12-27-2012 |
20140003117 | PINNING MAGNETIC DOMAIN WALLS IN A MAGNETIC DOMAIN SHIFT REGISTER MEMORY DEVICE | 01-02-2014 |
20140003118 | MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES | 01-02-2014 |
20140003119 | PINNING MAGNETIC DOMAIN WALLS IN A MAGNETIC DOMAIN SHIFT REGISTER MEMORY DEVICE | 01-02-2014 |
20140004625 | MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES | 01-02-2014 |
20140033516 | MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS - A method for fabricating a synthetic antiferromagnetic device, includes depositing a reference layer on a first tantalum layer and including depositing a first cobalt iron boron layer, depositing a second cobalt iron boron layer on the first cobalt iron boron layer, depositing a second Ta layer on the second cobalt iron boron layer, depositing a magnesium oxide spacer layer on the reference layer and depositing a cap layer on the magnesium oxide spacer layer. | 02-06-2014 |
20140037990 | MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS AND NON-PINNED REFERENCE LAYERS - A synthetic antiferromagnetic device includes a reference layer having a first and second ruthenium layer, a magnesium oxide spacer layer disposed on the reference layer, a cobalt iron boron layer disposed on the magnesium oxide spacer layer and a third ruthenium layer disposed on the cobalt iron boron layer, the third ruthenium layer having a thickness of approximately 0 angstroms to 18 angstroms. | 02-06-2014 |
20140037991 | MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS - A synthetic antiferromagnetic device includes a first tantalum layer, a reference layer disposed on the first tantalum layer and including a first cobalt iron boron layer, a second cobalt iron boron layer disposed on the first cobalt iron boron layer, a third cobalt iron boron layer and a second tantalum layer disposed between the second and third cobalt iron boron layers, a magnesium oxide spacer layer disposed on the reference layer and a cap layer disposed on the magnesium oxide spacer layer. | 02-06-2014 |
20140038309 | MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS AND NON-PINNED REFERENCE LAYERS - A method for fabricating a synthetic antiferromagnetic device, includes depositing a magnesium oxide spacer layer on a reference layer having a first and second ruthenium layer, depositing a cobalt iron boron layer on the magnesium oxide spacer layer; and depositing a third ruthenium layer on the cobalt iron boron layer, the third ruthenium layer having a thickness of approximately 0-18 angstroms. | 02-06-2014 |
20140126280 | MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION - A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance. | 05-08-2014 |
20140126281 | MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION - A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance. | 05-08-2014 |
20140138610 | MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICE READOUT - A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires. | 05-22-2014 |
20140141530 | MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICE READOUT - A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires. | 05-22-2014 |
20140160829 | METHOD AND APPARATUS FOR CONTROLLED APPLICATION OF OERSTED FIELD TO MAGNETIC MEMORY STRUCTURE - An apparatus for applying Oersted fields to a magnetic memory device comprises a first metal layer; a first insulating layer positioned on the first metal layer; a magnetic shift register wire positioned on the first insulating layer; a second insulating layer positioned on the magnetic shift register wire; a second metal layer positioned on the second insulating layer; a first conducting wire positioned in the first metal layer and extending transverse to the magnetic shift register wire; and a second conducting wire positioned in the second metal layer and extending transverse to the magnetic shift register wire. The first conducting wire is offset relative to the second conducting wire, the offset being defined by a distance between a first axis normal to the magnetic shift register wire and through the first conducting wire and a second axis normal to the magnetic shift register wire and through the second conducting wire. | 06-12-2014 |
20140353782 | THERMALLY ASSISTED MRAM WITH A MULTILAYER ENCAPSULANT FOR LOW THERMAL CONDUCTIVITY - A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction. | 12-04-2014 |
20140356979 | THERMALLY ASSISTED MRAM WITH A MULTILAYER ENCAPSULANT FOR LOW THERMAL CONDUCTIVITY - A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction. | 12-04-2014 |