Patent application number | Description | Published |
20150201373 | Data Transmission Method, User Equipment, and Network Side Device - The present invention provides a data transmission method, a user equipment, and a network side device. The method includes generating a concurrency policy, which is used to indicate a user equipment to select at least one access network from at least two access networks to transmit at least one data stream. The concurrency policy is sent to the user equipment through a first data connection between a first access network in the at least two access networks and the user equipment. | 07-16-2015 |
20150201410 | DATA SPLITTING METHOD AND DEVICE - A data splitting method is provided and includes: sending, by a first device, a data connection request to a second device, so that the second device executes data splitting; and receiving, by the first device through at least two radio links in multiple radio links, split data that is sent by the second device according to the data connection request, where the first device establishes, via a third device, one link of the at least two radio links with the second device, and the at least two radio links in the multiple radio links include two radio links that are established by using different radio protocols. According to the foregoing technical solutions, downlink data may be sent to a user equipment through different radio links in a splitting manner, thereby increasing downlink bandwidth allocated to a user, and improving user experience with data services. | 07-16-2015 |
20150223167 | Terminal, Wireless Network and Communication Methods with Low Power Consumption - Embodiments of the present invention provide a communication method of an MTC terminal with low power consumption, which includes: sending, by the MTC terminal, a wireless channel request message to a base station through a random access channel; receiving, by the MTC terminal, an immediate assignment message delivered by a wireless network; and sending, by the MTC terminal, an MTC data report message to the wireless network, where the MTC data report message includes a unique identifier of the MTC terminal, authentication information and service data. The embodiments of the present invention further provide an MTC terminal with low power consumption, and a communication method and system of a wireless network with low power consumption, which can reduce power consumption of a wireless terminal during communication, so that the MTC terminal can maintain communication for a longer period of time. | 08-06-2015 |
Patent application number | Description | Published |
20110279153 | HIGH-PRECISION OSCILLATOR SYSTEMS WITH FEED FORWARD COMPENSATION FOR CCFL DRIVER SYSTEMS AND METHODS THEREOF - System and method for generating one or more ramp signals. The method includes an oscillator configured to generate at least a clock signal, and a ramp signal generator configured to receive at least the clock signal and generate a first ramp signal. Additionally, the ramp signal generator is coupled to a first resistor including a first terminal and a second terminal. The first resistor is configured to receive an input voltage at the first terminal and is coupled to the ramp signal generator at the second terminal. Moreover, the first resistor is associated with a first resistance value. Also, the clock signal is associated with at least a predetermined frequency. The predetermined frequency does not change if the input voltage changes from a first magnitude to a second magnitude. The first magnitude is different from the second magnitude. | 11-17-2011 |
20110316428 | SYSTEMS AND METHODS FOR CONTROLLING BRIGHTNESS OF COLD-CATHODE FLUORESCENT LAMPS WITH WIDE DIMMING RANGE AND ADJUSTABLE MINIMUM BRIGHTNESS - System and method for adjusting brightness of one or more cold-cathode fluorescent lamps. The system includes a voltage selector configured to receive a dimming voltage and a first threshold voltage and generate an output voltage. The output voltage is selected from a group consisting of the dimming voltage and the first threshold voltage. Additionally, the system includes an oscillator coupled to a first capacitor and configured to generate a ramp signal with the first capacitor, and a signal generator configured to receive the ramp signal and the output voltage and generate a first signal. The first signal corresponds to a lamp brightness level. Moreover, the system includes a brightness detector configured to receive the first signal and output a second signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level. | 12-29-2011 |
20120268031 | SYSTEMS AND METHODS FOR DIMMING CONTROL WITH CAPACITIVE LOADS - System and method for dimming control. The system includes a system controller including a first controller terminal and a second controller terminal, a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, and a resistor including a first resistor terminal and a second resistor terminal. The system controller is configured to generate a first signal at the first controller terminal based on an input signal and to generate a second signal at the second controller terminal based on the first signal. The first transistor terminal is coupled to the second controller terminal. The first resistor terminal is coupled to the second transistor terminal. The second resistor terminal is coupled to the third transistor terminal. The transistor is configured to receive the second signal at the first transistor terminal and to change between two conditions in response to the second signal. | 10-25-2012 |
20120326629 | SYSTEMS AND METHODS FOR INTELLIGENT CONTROL OF COLD-CATHODE FLUORESCENT LAMPS - System and method for driving one or more cold-cathode fluorescent lamps. For example, the method includes generating at least one drive signal associated with a signal frequency, the signal frequency being equal to a first predetermined frequency, receiving a current-sensing signal, the current-sensing signal being associated with a lamp current for the one or more cold-cathode fluorescent lamps in response to at least the first predetermined frequency, and determining whether the current-sensing signal is larger than a first threshold in magnitude, the current-sensing signal being related to the first predetermined frequency. Additionally, the method includes, if the current-sensing signal related to the first predetermined frequency is determined to be larger than the first threshold in magnitude at anytime during a first period of time, changing the signal frequency from the first predetermined frequency to a second predetermined frequency, the second predetermined frequency being different from the first predetermined frequency. | 12-27-2012 |
20130033236 | SYSTEMS AND METHODS FOR DISCHARGING AN AC INPUT CAPACITOR WITH AUTOMATIC DETECTION - System and method for discharging a capacitor. An example system includes a signal detector and a discharge control component. The signal detector is configured to receive an input signal and generate a detection signal based on at least information associated with the input signal, the input signal being associated with an alternate current signal received by a capacitor including a first capacitor terminal and a second capacitor terminal. The discharge control component configured to receive at least the detection signal and generate an output signal to discharge the capacitor if the detection signal satisfies one or more conditions. | 02-07-2013 |
20130147357 | SYSTEMS AND METHODS FOR CONTROLLING BRIGHTNESS OF COLD-CATHODE FLUORESCENT LAMPS WITH WIDE DIMMING RANGE AND ADJUSTABLE MINIMUM BRIGHTNESS - System and method for adjusting brightness of one or more cold-cathode fluorescent lamps. The system includes a voltage selector configured to receive a dimming voltage and a first threshold voltage and generate an output voltage. The output voltage is selected from a group consisting of the dimming voltage and the first threshold voltage. Additionally, the system includes an oscillator coupled to a first capacitor and configured to generate a ramp signal with the first capacitor, and a signal generator configured to receive the ramp signal and the output voltage and generate a first signal. The first signal corresponds to a lamp brightness level. Moreover, the system includes a brightness detector configured to receive the first signal and output a second signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level. | 06-13-2013 |
20130147527 | HIGH-PRECISION OSCILLATOR SYSTEMS WITH FEED FORWARD COMPENSATION FOR CCFL DRIVER SYSTEMS AND METHODS THEREOF - System and method for generating one or more ramp signals. The method includes an oscillator configured to generate at least a clock signal, and a ramp signal generator configured to receive at least the clock signal and generate a first ramp signal. Additionally, the ramp signal generator is coupled to a first resistor including a first terminal and a second terminal. The first resistor is configured to receive an input voltage at the first terminal and is coupled to the ramp signal generator at the second terminal. Moreover, the first resistor is associated with a first resistance value. Also, the clock signal is associated with at least a predetermined frequency. The predetermined frequency does not change if the input voltage changes from a first magnitude to a second magnitude. The first magnitude is different from the second magnitude. | 06-13-2013 |
20140233271 | SYSTEMS AND METHODS FOR REDUCING ELECTROMAGNETIC INTERFERENCE BY ADJUSTING SWITCHING PROCESSES - System and method for regulating a power conversion system. An example system controller for regulating a power conversion system includes a signal generator and a driving component. The signal generator is configured to receive a feedback signal associated with an output signal of a power conversion system and a current sensing signal associated with a primary current flowing through a primary winding of the power conversion system and generate a modulation signal based on at least information associated with the feedback signal and the current sensing signal. The driving component is configured to receive the modulation signal and output a drive signal to a switch based on at least information associated with the modulation signal. | 08-21-2014 |
20150091470 | SYSTEMS AND METHODS FOR DIMMING CONTROL WITH CAPACITIVE LOADS - System and method for dimming control. The system includes a system controller including a first controller terminal and a second controller terminal, a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, and a resistor including a first resistor terminal and a second resistor terminal. The system controller is configured to generate a first signal at the first controller terminal based on an input signal and to generate a second signal at the second controller terminal based on the first signal. The first transistor terminal is coupled to the second controller terminal. The first resistor terminal is coupled to the second transistor terminal. The second resistor terminal is coupled to the third transistor terminal. The transistor is configured to receive the second signal at the first transistor terminal and to change between two conditions in response to the second signal. | 04-02-2015 |
20160036336 | SYSTEMS AND METHODS FOR REDUCING ELECTROMAGNETIC INTERFERENCE BY ADJUSTING SWITCHING PROCESSES - System and method for regulating a power conversion system. An example system controller for regulating a power conversion system includes a signal generator and a driving component. The signal generator is configured to receive a feedback signal associated with an output signal of a power conversion system and a current sensing signal associated with a primary current flowing through a primary winding of the power conversion system and generate a modulation signal based on at least information associated with the feedback signal and the current sensing signal. The driving component is configured to receive the modulation signal and output a drive signal to a switch based on at least information associated with the modulation signal. | 02-04-2016 |
Patent application number | Description | Published |
20150087235 | Communication Method and Apparatus for NFC Device and NFC Device - A communication method and apparatus for a near field communication (NFC) device and the NFC device, where the method includes determining a radio frequency (RF) protocol supported by at least one discovered target NFC device; and selecting, according to an RF protocol level or an RF protocol priority, an RF protocol for performing NFC from the RF protocol supported by the at least one target NFC device so as to perform communication with a target NFC device corresponding to the RF protocol determined by selection. The communication method and apparatus provided in the embodiments of the present invention solve a problem that a probability of finding a target NFC device matched with an NFC controller (NFCC) chip function on a local NFC device is low and a problem that device host (DH) resource consumption and power consumption incurred thereof are high. | 03-26-2015 |
20150105015 | Method, Apparatus, and Terminal Device for Near Field Communication Radio Frequency Communication - A method for near field communication (NFC) radio frequency communication includes acquiring, second configuration information of established radio frequency communication, where the established radio frequency communication is radio frequency communication that a second NFC host performs with a remote NFC endpoint using a near field communication controller (NFCC); and if the second configuration information matches first configuration information of radio frequency communication to be initiated by the first NFC host, sending, to the NFCC, an activate request command used to activate a radio frequency interface corresponding to the first configuration information, so that the NFCC activates the radio frequency interface and the first NFC host performs the radio frequency communication with the remote NFC endpoint through the radio frequency interface. The embodiments of the present invention provide a radio frequency communication mechanism for an NFC device under a multi-host architecture. | 04-16-2015 |
20150112860 | Contactless Payment Method, Device, and System - The present invention provides a contactless payment method, device, and system. After a mobile terminal having an NFC function receives, from a reading terminal, a selection command including a financial document application identifier, the mobile terminal returns, if it is determined that a supplementary payment application needs to be executed, a PPSE corresponding to the financial document application identifier to the reading terminal, where the PPSE includes a first application identifier that indicates a bank payment application and a second application identifier that indicates a supplementary payment application, and a priority of the second application identifier is higher than a priority of the first application identifier, so that the reading terminal acquires, according to priorities of payment applications in the PPSE, payment information corresponding to the payment applications from the mobile terminal in sequence to complete payment, thereby improving efficiency of contactless payment. | 04-23-2015 |
20150140928 | METHOD, APPARATUS, AND TERMINAL DEVICE FOR CONTROLLING NEAR FIELD COMMUNICATION RADIO FREQUENCY DISCOVERY - A method for controlling near field communication radio frequency discovery. The method includes: acquiring, by a first NFC host, state information used to indicate a state of a near field communication controller NFCC; and skipping, by the first NFC host, sending a first radio frequency discovery command to the NFCC if the state of the NFCC is non-idle; or if the state of the NFCC is non-idle, and a priority of the first NFC host is higher than a priority of a third NFC host, sending, by the first NFC host, a state resetting command to the NFCC, so that the NFCC terminates a current radio frequency communication process. The embodiments of the present invention provide a radio frequency communication mechanism of an NFC device in a multi-host architecture. | 05-21-2015 |
20150142589 | Method, Mobile Terminal and POS Machine for Implementing Selection of Secure Element in Near Field Communication - A method, a mobile terminal, and a point of sale (POS) machine for implementing selection of a secure element in near field communication are provided. The method includes receiving, by a near field communication controller on a local end, a first configuration instruction sent by a device host on the local end, where the first configuration instruction includes an environment characteristic used for selecting the secure element; configuring, by the near field communication controller, the environment characteristic in the near field communication controller according to the first configuration instruction; receiving, by the near field communication controller, a second configuration instruction sent by the device host; and configuring, by the near field communication controller according to the second configuration instruction, the environment characteristic in an attribute response instruction for communicating and interacting with a peer end. | 05-21-2015 |
20150147966 | Near Field Communication Method and Near Field Communication Device - A near field communication method and a near field communication device are provided. The near field communication method includes that a second device acquires a near field communication identification (NFCID) of a first device, where the NFCID of the first device carries first device type/device capability (DT) information, and the first DT information is used to indicate a device type/device capability supported by the first device; and the second device extracts the first DT information from the NFCID of the first device. According to the embodiments of the present invention, an NFCID of a near field communication device carries information about a device type/device capability supported by the near field communication device, so that exchanging or searching of a device type/device capability can be implemented by using the NFCID. | 05-28-2015 |
Patent application number | Description | Published |
20150041111 | Heat Exchange Plate, Heat Exchanger, and Communication Base Station Cabinet - The present invention discloses a heat exchange plate, heat exchanger, and communication base station cabinet. The heat exchange plate includes a heat exchange plate body that has an air duct, an air inlet is disposed on a first side surface of the heat exchange plate body and an air outlet is disposed on an adjacent second side surface of the heat exchange plate body. The air duct is formed between the air inlet and the air outlet, and a diversion structure for guiding air to flow is disposed in the air duct. | 02-12-2015 |
20150327004 | NFC Configuration Method, NFC Data Transmission Method, Controller, and NFC Controller - An NFC configuration method. A controller sends data and a parameter of the data to an NFC module for storage or sends a storage space application instruction to an NFC module, such that storage space is reserved for data in the NFC module. Therefore, when data is sent or received in an NFC High manner, the sent data can be acquired from the NFC module or the received data can be stored in the NFC module without participation of a DH, thereby reducing load of the DH. | 11-12-2015 |
20160037413 | CONNECTION HANDOVER METHOD BASED ON NEAR FIELD COMMUNICATION, AND CORRESPONDING APPARATUS - The present invention discloses a connection handover method for near field communication, and further disclose a connection handover apparatus. The method includes: acquiring, by a zeroth terminal, idle connection resource information of the zeroth terminal; receiving a request message that is sent by a first terminal and is used for initiating a connection handover process or used for notifying the zeroth terminal that a connection handover process needs to be performed; and determining, according to the request message, that the following determining needs to be performed: determining, according to the idle connection resource information of the zeroth terminal, whether the zeroth terminal has an idle connection resource, if yes, sending a response message to the first terminal, so as to feed back connection configuration information of the zeroth terminal to the first terminal, and if not, skipping feeding back connection configuration information of the zeroth terminal to the first terminal. | 02-04-2016 |
20160105925 | NFC RADIO FREQUENCY COMMUNICATION CONTROL METHOD, APPARATUS, AND SYSTEM - An near field communication (NFC) radio frequency communication control method. The method includes: instructing, by a first NFC host by using a second message, an NFCC to terminate, according to the second message, a radio frequency communication process currently executed for a third NFC host after the first NFC receives a first message used to indicate that a second NFC host requests radio frequency communication and when the first NFC determines that the NFCC is currently in a non-idle state and a priority of the second NFC host is higher than a priority of the third NFC host, where the third NFC host is an NFC host corresponding to the radio frequency communication process currently executed by the NFCC. This effectively avoids the problem that a conflict occurs when multiple NFC hosts request radio frequency communication from an NFCC in an NFC multi-host architecture, thereby maintaining system running reliability. | 04-14-2016 |
Patent application number | Description | Published |
20120139044 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI wafer, which comprises a bottom semiconductor substrate, a first buried insulating layer on the bottom semiconductor substrate, and a first semiconductor layer on the first buried insulating layer; a source region and a drain region which are formed in a second semiconductor layer over the SOI wafer, wherein there is a second buried insulating layer between the second semiconductor layer and the SOI wafer; a channel region, which is formed in the second semiconductor layer and located between the source region and the drain regions; and a gate stack, which comprises a gate dielectric layer on the second semiconductor layer and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the first semiconductor substrate below the channel region, the backgate having a non-uniform doping profile, and the second buried insulating layer serving as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the polarity of dopants and/or the doping profile in the backgate. Leakage in the semiconductor device can be reduced. | 06-07-2012 |
20120139048 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI chip comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; source/drain regions formed in the semiconductor layer; a channel region formed in the semiconductor layer and located between the source/drain regions; and a gate stack comprising a gate dielectric layer on the semiconductor layer, and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the semiconductor substrate below the channel region, and the backgate has a non-uniform doping profile, and wherein the buried insulating layer serves as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the type of dopant and/or the doping profile in the backgate, and reduces a leakage current of the semiconductor device. | 06-07-2012 |
20120326231 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer, which comprises a semiconductor substrate, a buried insulator layer, and a semiconductor layer, the buried insulator layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulator layer; a gate stack, which is disposed on the semiconductor layer; a source region and a drain region, which are disposed in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which are disposed in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate disposed in the semiconductor substrate, and wherein the back gate comprises first, second and third compensation doping regions, the first compensation doping region is disposed under the source region and the drain region; the second compensation doping region extends in a direction away from the channel region and adjoining the first compensation doping region; and the third compensation doping region is disposed under the channel region and adjoining the first compensation doping region. By changing the doping type of the back gate, the MOSFET can have an adjustable threshold voltage, and can have a reduced parasitic capacitance and a reduced contact resistance in connection with the back gate. | 12-27-2012 |
20130001665 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate. | 01-03-2013 |
20130099315 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate. The MOSFET can adjust the threshold voltage by changing the doping type and doping concentration of the anti-doped region. | 04-25-2013 |
20150200275 | FINFET AND METHOD FOR MANUFACTURING THE SAME - A FinFET with reduced leakage between source and drain regions, and a method for manufacturing the FinFET are disclosed. In one aspect, the method includes forming, on a semiconductor substrate, at least two openings to define a semiconductor fin. The method also includes forming a gate dielectric layer that conformally covers the fin and the openings. The method also includes forming, within the openings, a first gate conductor adjacent to the bottom of the fin. The method also includes forming, within the openings, an insulating isolation layer on the first gate conductor. The method also includes forming a second gate conductor on the fin and on the insulating isolation layer adjacent to the top of the fin. The method also includes forming spacers on sidewalls of the second gate conductor. The method also includes forming a source region and a drain region in the fin. | 07-16-2015 |
20150221769 | FINFET AND METHOD FOR MANUFACTURING THE SAME - An FinFET and a method for manufacturing the same are disclosed. The FinFET comprises: a semiconductor substrate; a stress layer on the semiconductor substrate; a semiconductor fin on the stress layer, the semiconductor fin having two sidewalls extending in its length direction; a gate dielectric on the sidewalls of the semiconductor fin; a gate conductor on the gate dielectric; and a source region and a drain region at two ends of the semiconductor fin, wherein the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin. | 08-06-2015 |
20150255609 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions. | 09-10-2015 |
20150287828 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack. | 10-08-2015 |
20150294879 | METHOD FOR MANUFACTURING FIN STRUCTURE - Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin. | 10-15-2015 |
20150325699 | FINFET AND METHOD FOR MANUFACTURING THE SAME - A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack. | 11-12-2015 |
Patent application number | Description | Published |
20110092118 | Curable Aqueous Composition - A curable aqueous composition, a method for forming a treated substrate with the curable aqueous composition, and the substrate so treated are provided. The curable aqueous composition, the process for forming a treated substrate and the treated substrate may be free from formaldehyde. The curable aqueous composition includes: an emulsion polymer including, as copolymerized units, from 0.5 to 9% ethylenically-unsaturated dicarboxylic acid monomer by weight, based on the weight of the emulsion polymer; and a polyol in the amount of from 0.5 to 15%, by weight, based on the weight of the emulsion polymer, wherein the aqueous composition includes carboxylic acid-containing polymer including, as polymerized units, from 0.5 to 9% carboxylic acid monomer by weight, based on the total weight of the carboxylic acid-containing polymer. | 04-21-2011 |
20110152447 | Curable Aqueous composition - A curable aqueous composition, a method for forming a treated substrate with the curable aqueous composition, and the substrate so treated are provided. The composition, the method and the treated substrate may be free from formaldehyde. The composition comprises a (co)polymer and a crosslinker, said (co)polymer comprising, as (co)polymerized units, from 0.05 to 10 wt %, based on the dry weight of the composition, ethylenically unsaturated monomer having at least two carboxylic acid groups, wherein the crosslinker having at least two hydrazino groups having a molar ratio of at least 0.05 of the carboxylic acid group, and wherein the aqueous composition is curable at a temperature of from 100° C. to 250° C. | 06-23-2011 |
20120251822 | Clean Removable Adhesive Sheet - The invention provides an adhesive sheet comprising polyvinyl chloride (PVC) film and back coating of water based PSA, wherein said PSA comprises a copolymer by copolymerization of a monomer mixture comprising, a) from 30 wt % to less than 70 wt % acrylic acid C4-C8-alkylester, and b) from 2 wt % to 9 wt % (meth)acrylonitrile, wherein the polyvinyl chloride film is not corona treated. The adhesive sheet is suitable for applications of indoor and outdoor graphic poster, especially for clean removable usages. | 10-04-2012 |
Patent application number | Description | Published |
20110248354 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects. | 10-13-2011 |
20110254013 | HYBRID ORIENTATION ACCUMULATION MODE GAA CMOSFET - A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased. | 10-20-2011 |
20110254099 | Hybrid material accumulation mode GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
20110254100 | HYBRID MATERIAL ACCUMULATION MODE GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented. | 10-20-2011 |
20110254101 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
20110254102 | HYBRID ORIENTATION INVERSION MODE GAA CMOSFET - A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects. | 10-20-2011 |
20120112283 | ESD PROTECTION DEVICES FOR SOI INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness. | 05-10-2012 |
20120129320 | METHOD OF NISIGE EPITAXIAL GROWTH BY INTRODUCING AL INTERLAYER - The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance. | 05-24-2012 |
20130029478 | METHOD OF FABRICATING HIGH-MOBILITY DUAL CHANNEL MATERIAL BASED ON SOI SUBSTRATE - The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation. | 01-31-2013 |
20130062696 | SOI Semiconductor Structure with a Hybrid of Coplanar Germanium and III-V, and Preparation Method thereof - The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor. The preparation method for forming the semiconductor structure includes: preparing a global Ge on insulator substrate structure; preparing a group III-V semiconductor material layer on the Ge on insulator substrate structure; performing photolithography and etching for the first time to make a patterned window to the above of a Ge layer to form a recess; preparing a spacer in the recess; preparing a Ge film by selective epitaxial growth; performing a chemical mechanical polishing to obtain the heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material being coplanar; removing the spacer and a defective Ge layer part close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high-performance CMOS device including a Ge PMOS and a III-V NMOS by forming an MOS structure. | 03-14-2013 |
20130071993 | Preparation Method for Full-Isolated SOI with Hybrid Crystal Orientations - A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer. The top silicon and the insulating buried layer formed in the method have uniform and controllable thickness, the strained silicon formed in the window and the top silicon outside the window have different crystal orientations, so as to provide higher mobility for the NMOS and the PMOS respectively, thereby improving the performance of the CMOS IC. | 03-21-2013 |
20130105631 | ICING DETECTOR PROBE AND ICING DETECTOR WITH THE SAME | 05-02-2013 |
20130113926 | DETECTING DEVICE FOR DETECTING ICING BY IMAGE AND DETECTING METHOD THEREOF - A detecting device for detecting icing by an image includes an image acquiring system ( | 05-09-2013 |
20130221412 | Device System Structure Based On Hybrid Orientation SOI and Channel Stress and Preparation Method Thereof - The present invention provides a device system structure based on hybrid orientation SOI and channel stress and a preparation method thereof. According to the preparation method provided in the present invention, first, a (100)/(110) global hybrid orientation SOI structure is prepared; then, after epitaxially growing a relaxed silicon-germanium layer and strained silicon layer sequentially on the global hybrid orientation SOI structure, an (110) epitaxial pattern window is formed; then, after epitaxially growing a (110) silicon layer and a non-relaxed silicon-germanium layer at the (110) epitaxial pattern window, a surface of the patterned hybrid orientation SOI structure is planarized; then, an isolation structure for isolating devices is formed; and finally, a P-type high-voltage device structure is prepared in a (110) substrate portion, an N-type high-voltage device structure and/or low voltage device structures are prepared in the (100) substrate portion. In this manner, a carrier mobility is improved, Rdson of a high-voltage device is reduced, and performance of devices are improved, thereby facilitating further improvement of integration and reduction of power consumption. | 08-29-2013 |
20130264609 | Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof - The present invention provides a semiconductor structure with a hybrid of Ge and a group III-V material coplanar and a preparation method thereof. A heterogeneously integrated semiconductor structure with Ge and a group III-V semiconductor material coplanar includes at least one Ge substrate formed on a bulk silicon substrate, and the other substrate is the group III-V semiconductor material formed on the Ge semiconductor. The preparation method includes: preparing a Ge semiconductor layer on a bulk silicon substrate; preparing a group III-V semiconductor material layer on the Ge semiconductor layer; performing first photolithography and etching to make a patterned window to a Ge layer so as to form a recess; preparing a spacer in the recess; preparing a Ge film through selective epitaxial growth; performing chemical mechanical polishing to obtain a heterogeneously integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar; removing the spacer and a defect part of the Ge layer close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high performance CMOS device including a Ge channel PMOS and a group III-V channel NMOS by forming an MOS structure. | 10-10-2013 |
20130273714 | METHOD FOR PREPARING SEMICONDUCTOR SUBSTRATE WITH INSULATING BURIED LAYER BY GETTERING PROCESS - A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded. | 10-17-2013 |
20140004684 | Method for Preparing GOI Chip Structure | 01-02-2014 |
20140199825 | SILICON-GERMANIUM HETEROJUNCTION TUNNEL FIELD EFFECT TRANSISTOR AND PREPARATION METHOD THEREOF - A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects. The preparation method according to the present invention has a simple process, which is compatible with the CMOS process and is applicable to mass industrial production. | 07-17-2014 |
20140349556 | WORKING TOOL - A working tool includes a housing ( | 11-27-2014 |
20150194338 | Method For Preparing Ultra-thin Material On Insulator Through Adsorption By Doped Ultra-thin Layer - The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small. In addition, an impurity atom strengthens an ion adsorption capability of the ultra-thin single crystal film, so that an ion implantation dose and the annealing temperature can be lowered in the preparation procedure, thereby effectively reducing the damage caused by the implantation to the top film, and achieving objectives of improving production efficiency and reducing the production cost. | 07-09-2015 |
20150325468 | METHOD FOR PREPARING MATERIAL ON INSULATOR BASED ON ENHANCED ADSORPTION - Provided is a method for preparing a material on an insulator based on enhanced adsorption. In the method: first, a single crystal film having a doped superlattice structure, an intermediate layer, a buffer layer and a top layer film are epitaxially grown in succession on a first substrate; then, low dosage ion implantation is performed on the structure on which the top layer film is formed, so that ions are implanted above an upper surface or below a lower surface of the single crystal film having a doped superlattice structure; next, a second substrate having an insulation layer is bonded to the structure on which ion implantation has already been performed, and an annealing treatment is performed, so that a microscopic crack is produced at the single crystal film having a doped superlattice structure to achieve atomic-scale stripping. The effective stripping of bonding wafers is achieved by means of enhanced adsorption. The stripped surface is smooth and has a low roughness, and the quality of the crystal of the top layer film is high. | 11-12-2015 |
20160005609 | MANUFACTURING METHOD OF GRAPHENE MODULATED HIGH-K OXIDE AND METAL GATE MOS DEVICE - A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeO | 01-07-2016 |
20160114897 | Airplane Suspension Cowling Structure With Wing-Mounted Arrangement - Provided is an airplane suspension ( | 04-28-2016 |