Patent application number | Description | Published |
20110191913 | CELLS PRODUCING GLYCOPROTEINS HAVING ALTERED GLYCOSYLATION PATTERNS AND METHOD AND USE THEREOF - The present application relates to the field of glyco-engineering, more specifically to eukaryotic cells wherein both an endoglucosaminidase and a glycoprotein are present. These cells can be used to deglycosylate or partly deglycosylate the (exogenous) glycoprotein, in particular without the need for adding an extra enzyme. Methods are also provided for the application of these cells in protein production. According to one specific aspect, the eukaryotic cells and methods are glyco-engineered yeast cells in which additionally at least one exogenous enzyme needed for complex glycosylation is present, e.g. allowing easier separation of differentially glycosylated glycoproteins. | 08-04-2011 |
20140345004 | CELLS PRODUCING GLYCOPROTEINS HAVING ALTERED GLYCOSYLATION PATTERNS AND METHOD AND USE THEREOF - The disclosure relates to the field of glyco-engineering, more specifically, to eukaryotic cells wherein both an endoglucosaminidase and a glycoprotein are present. These cells can be used to deglycosylate or partly deglycosylate the (exogenous) glycoprotein, in particular, without the need for adding an extra enzyme. Methods are also provided for the application of these cells in protein production. According to one specific aspect, the eukaryotic cells are glyco-engineered yeast cells in which, additionally, at least one exogenous enzyme needed for complex glycosylation is present, e.g., allowing easier separation of differentially glycosylated glycoproteins. | 11-20-2014 |
Patent application number | Description | Published |
20080214013 | Method for Removal of Bulk Metal Contamination from III-V Semiconductor Substrates - The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 μm×2 μm) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device. | 09-04-2008 |
20090085167 | Methods for Forming Metal-Germanide Layers and Devices Obtained Thereby - The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO | 04-02-2009 |
20090283756 | SCALABLE QUANTUM WELL DEVICE AND METHOD FOR MANUFACTURING THE SAME - A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap. | 11-19-2009 |
20100065824 | METHOD FOR REDUCING FERMI-LEVEL-PINNING IN A NON-SILICON CHANNEL MOS DEVICE - A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created. | 03-18-2010 |
20110140087 | SCALABLE QUANTUM WELL DEVICE AND METHOD FOR MANUFACTURING THE SAME - A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap. | 06-16-2011 |
20150125987 | METHOD FOR CLEANING AND PASSIVATING CHALCOGENIDE LAYERS - A method for chemically cleaning and passivating a chalcogenide layer is provided, wherein the method comprises bringing the chalcogenide layer into contact with an ammonium sulfide containing ambient, such as an ammonium sulfide liquid solution or an ammonium sulfide containing vapor. Further, a method for fabricating photovoltaic cells with a chalcogenide absorber layer is provided, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; bringing the chalcogenide semiconductor layer into contact with an ammonium sulfide containing ambient, thereby removing impurities and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer. | 05-07-2015 |