Patent application number | Description | Published |
20100199154 | Reduced processing in high-speed Reed-Solomon decoding - Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift. | 08-05-2010 |
20110125959 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored. | 05-26-2011 |
20110239085 | ECC WITH OUT OF ORDER COMPLETION - Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder. | 09-29-2011 |
20120081971 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits. | 04-05-2012 |
20130208540 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - An instruction to perform an erase on a group of one or more memory cells is sent. An indication that the erasure of the group of memory cells is unsuccessful is received. In response to receiving the indication that the erasure of the group of memory cells is unsuccessful, the value of a voltage threshold, associated with the group of memory cells, is changed to a new voltage threshold and the new voltage threshold and identification information associated with the group of memory cells is stored. | 08-15-2013 |
20140219033 | FLASH MULTIPLE-PASS WRITE WITH ACCURATE FIRST-PASS WRITE - An indication to store a data value in Flash memory is received. An accurate coarse write is performed on the Flash memory, including by: storing a first voltage level in the Flash memory and setting a configuration setting of the Flash memory to a first setting. The first voltage level, when interpreted using the configuration setting at the first setting, corresponds to the data value. A fine write is performed on the Flash memory, including by: storing a second voltage level in the Flash memory and setting the configuration setting of the Flash memory to a second setting. The second voltage level, when interpreted using the configuration setting at the second setting, corresponds to the data value. | 08-07-2014 |
20140365716 | INTERFACE BETWEEN MULTIPLE CONTROLLERS - A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface. | 12-11-2014 |
20140376314 | FLASH MULTIPLE-PASS WRITE WITH ACCURATE FIRST-PASS WRITE - An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction. | 12-25-2014 |