| Patent application number | Description | Published |
|---|
| 20090031070 | Systems And Methods For Improving Performance Of A Routable Fabric - Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric. | 01-29-2009 |
| 20090080164 | MEMORY SYSTEM AND METHOD - A system in some embodiments includes a system having a memory module having a first board comprising a first plurality of memory receptacles configured to support a first plurality of in-line memory modules in an overlapping relationship with a second plurality of in-line memory modules disposed on a second board. Further, a method in some embodiments includes rotating first and second memory boards into a parallel configuration via a hinge coupling the first and second memory boards, and inserting the first and second memory boards into first and second board connectors simultaneously. | 03-26-2009 |
| 20110115454 | VOLTAGE REGULATOR - A voltage regulator is provided that includes current sense circuitry configured to detect an amount of current provided to a load, a voltage controlled oscillator configured to output a clock signal with a constant duty cycle at a frequency that varies in dependence on the amount of current detected by current sense circuitry, and regulator circuitry configured to provide a regulated voltage to the load using the clock signal. | 05-19-2011 |
| 20120110363 | METHOD AND SYSTEM FOR POWER-EFFICIENT AND NON-SIGNAL-DEGRADING VOLTAGE REGULATION IN MEMORY SUBSYSTEMS - Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate. | 05-03-2012 |
| 20130326293 | MEMORY ERROR TEST ROUTINE - An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure is to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored. | 12-05-2013 |
| 20140359181 | Delaying Bus Activity To Accomodate Memory Device Processing Time - A technique includes delaying bus activity targeting a memory device and indicating a command for the memory device to allow time for the memory device to complete processing the command. The delaying of the bus activity includes selectively generating an error signal on a memory bus. | 12-04-2014 |
| 20140372682 | NONVOLATILE MEMORY BANK GROUPS - A nonvolatile memory ( | 12-18-2014 |
| 20150095564 | APPARATUS AND METHOD FOR SELECTING MEMORY OUTSIDE A MEMORY ARRAY - An apparatus includes a memory module, which includes a memory array. The memory array includes rows of memory and columns of memory. The apparatus also includes at least one row of memory not in the memory array and a register. The register includes an address space and a row/column indicator. The apparatus also includes row selection logic to select the at least one row to be activated if the address from an address bus equals the register value and if the row/column indicator indicates row. | 04-02-2015 |
