Patent application number | Description | Published |
20110011802 | SYSTEMS AND METHODS FOR SIMULTANEOUSLY GENERATING ENERGY AND TREATING WATER - A system that enables cooling a concentrated photovoltaic cell, while simultaneously treating water, e.g., desalinating sea water. A concentrated PV panel converts solar energy to electric power. Recirculated water e.g., reclaimed or sea water, at an optimized temperature range flows into the PV panel to cool the solar PV cells. The recirculated water is heated by the PV panel and is then directed to a water treatment unit, e.g., a heat exchanger or water desalinator. The water treatment unit may be a high temperature reverse osmosis (RO) unit, or a bacterial water treatment plant. A flow of water to be treated enters the heat exchanger/desalinator unit. Heat from the heated recirculated water is used to treat the cooler water. | 01-20-2011 |
20150349145 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349161 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349162 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349168 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349170 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349171 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349172 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349173 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349174 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349175 | SHINGLED SOLAR CELL PANEL EMPLOYING HIDDEN TAPS - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency | 12-03-2015 |
20150349176 | HIGH VOLTAGE SOLAR PANEL - A high voltage solar cell module comprises silicon solar cells arranged in a shingled manner to form super cells. A solar photovoltaic system may comprise two or more such high voltage solar cell modules electrically connected in parallel with each other and to an inverter. | 12-03-2015 |
20150349190 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349701 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349702 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
20150349703 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 12-03-2015 |
Patent application number | Description | Published |
20090125866 | METHOD FOR PERFORMING PATTERN DECOMPOSITION FOR A FULL CHIP DESIGN - A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph. | 05-14-2009 |
20090172630 | AUTOMATED PROCESSOR GENERATION SYSTEM AND METHOD FOR DESIGNING A CONFIGURABLE PROCESSOR - A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification. | 07-02-2009 |
20090177876 | AUTOMATED PROCESSOR GENERATION SYSTEM AND METHOD FOR DESIGNING A CONFIGURABLE PROCESSOR - A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification. | 07-09-2009 |
20100287622 | System and Method for Preventing Proper Execution of an Application Program in an Unauthorized Processor - A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling program to the application program such that when the program is running in a processor, it retrieves a second identifier from the processor and unscrambles the scrambled portion of the application program using the retrieved second identifier. If the second identifier does not correspond to an authorized processor design, the unscrambling operation will incorrectly unscramble the scrambled portion and the application program will not run properly. | 11-11-2010 |
20140189231 | Audio Digital Signal Processor - A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation. | 07-03-2014 |
Patent application number | Description | Published |
20080209181 | Method and System for Automatic Generation of Processor Datapaths - Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. In addition, certain aspects may take one or more operations as well as one or more input semantics and either re-implement the input semantics automatically, or combine the input semantics with each other or with one or more other operations to automatically generate a new set of shared processor datapaths. | 08-28-2008 |
20080244471 | SYSTEM AND METHOD OF CUSTOMIZING AN EXISTING PROCESSOR DESIGN HAVING AN EXISTING PROCESSOR INSTRUCTION SET ARCHITECTURE WITH INSTRUCTION EXTENSIONS - An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development. | 10-02-2008 |
20080244506 | SYSTEM AND METHOD OF DESIGNING INSTRUCTION EXTENSIONS TO SUPPLEMENT AN EXISTING PROCESSOR INSTRUCTION SET ARCHITECTURE - An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development. | 10-02-2008 |
20120185808 | Method and System for Automatic Generation of Processor Datapaths - Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. | 07-19-2012 |